[Mesa-dev] [Bug 90264] [Regression, bisected] Tooltip corruption in Chrome

https://bugs.freedesktop.org/show_bug.cgi?id=90264 --- Comment #24 from Boyan Ding --- Furkan, try launching chrome with LIBGL_DRI3_DISABLE=1 and see if the problem still persist. The problem at least went away on my machine when I disable DRI3. -- You are receiving this mail because: You are t

[Mesa-dev] [Bug 90264] [Regression, bisected] Tooltip corruption in Chrome

https://bugs.freedesktop.org/show_bug.cgi?id=90264 --- Comment #25 from Furkan --- I forgot to add, I have DRI3 disabled already. From my Xorg log: [12.974] (II) RADEON(0): [DRI2] Setup complete [12.974] (II) RADEON(0): [DRI2] DRI driver: radeonsi [12.974] (II) RADEON(0): [DRI2]

Re: [Mesa-dev] [PATCH v2 09/19] i965/fs: Add a builder argument to offset()

On Thu, Jun 25, 2015 at 01:24:53PM -0700, Jason Ekstrand wrote: > --- > src/mesa/drivers/dri/i965/brw_fs.cpp | 42 > src/mesa/drivers/dri/i965/brw_fs.h | 2 +- > src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 2 +- > src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 5

[Mesa-dev] [Bug 90264] [Regression, bisected] Tooltip corruption in Chrome

https://bugs.freedesktop.org/show_bug.cgi?id=90264 --- Comment #26 from Eero Tamminen --- (In reply to Matt Whitlock from comment #15) > (In reply to Furkan from comment #14) > > For those of you who are using nouveau, does the problem go away after > > reverting the mesa commit that I bisected?

Re: [Mesa-dev] [PATCH] i965/gen6: Set up layer constraints properly for depth buffers.

On Thu, Jun 25, 2015 at 09:17:38AM -0700, Kenneth Graunke wrote: > This ports over Chris Forbes' equivalent fixes in gen7_misc_state.c > from commit 77d55ef4819436ebbf9786a1e720ec00707bbb19. > > No Piglit changes on Sandybridge. > > Signed-off-by: Kenneth Graunke Reviewed-by: Topi Pohjolainen

Re: [Mesa-dev] [PATCH 3/6] i965: Enable hardware-generated binding tables on render path.

On Fri, Jun 26, 2015 at 08:51:59AM +0300, Abdiel Janulgue wrote: > This patch implements the binding table enable command which is also > used to allocate a binding table pool where where hardware-generated > binding table entries are flushed into. Each binding table offset in > the binding table p

[Mesa-dev] [PATCH v3] mesa: Do not give ralloc_strcat a NULL

From: Marta Lofstedt When a program is compiled, but linking failed the sh->InfoLog could be NULL. This is exploited by OpenGL ES 3.1 conformance tests. V3: Chnaged title. Signed-off-by: Marta Lofstedt --- src/mesa/main/shaderapi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff

Re: [Mesa-dev] [PATCH v2] mesa : NULL check InfoLog

> -Original Message- > From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On > Behalf Of Matt Turner > Sent: Friday, June 26, 2015 1:40 AM > To: Ben Widawsky > Cc: mesa-dev@lists.freedesktop.org > Subject: Re: [Mesa-dev] [PATCH v2] mesa : NULL check InfoLog > > On Thu, Jun 25

Re: [Mesa-dev] [PATCH 5/6] i965: Upload binding tables in hw-generated binding table format.

On Fri, Jun 26, 2015 at 08:52:01AM +0300, Abdiel Janulgue wrote: > When hardware-generated binding tables are enabled, use the hw-generated > binding table format when uploading binding table state. > > Normally, the CS will will just consume the binding table pointer commands > as pipelined state

[Mesa-dev] [PATCH 02/78] i965/nir/vec4: Select between new nir_vec4 or current vec4_visitor code-paths

The NIR->vec4 pass will be activated if ALL the following conditions are met: * INTEL_USE_NIR environment variable is defined and is positive (1 or true) * The stage is vertex shader * The HW generation is either SandyBridge (gen6), IvyBridge or Haswell (gen7) Bugzilla: https://bugs.freedesktop.o

[Mesa-dev] [PATCH 00/78] i965: A new vec4 backend based on NIR

Hello, This series adds a new vec4 backend for i965 based on NIR. It is the result of working on https://bugs.freedesktop.org/show_bug.cgi?id=89580. This backend is activated if all the following conditions are met: * INTEL_USE_NIR environment variable is set to 1 (or true) * The stage is a GLS

[Mesa-dev] [PATCH 01/78] i965/nir/vec4: Add implementation placeholders for a new NIR->vec4 pass

This patch will add a brw_vec4_nir.cpp file filled with entry point methods to the main functionality, following a structure similar to brw_fs_nir.cpp. Subsequent patches in this series will be adding the implementations for these methods, incrementally. Bugzilla: https://bugs.freedesktop.org/sho

[Mesa-dev] [PATCH 04/78] i965/nir/vec4: Add setup of input variables in NIR->vec4 pass

This implementation sets up a map of input variable offsets to source registers that are already initialized with the corresponding register offset. This map will then be queried when processing load_input intrinsic operations, to obtain the correct register source from which the input data will b

[Mesa-dev] [PATCH 03/78] i965/vec4: Move type_size() method to brw_vec4_visitor class

The type_size() method is currently accessible only in the implementation of vec4_visitor. Since we need to reuse it in the upcoming NIR->vec4 pass, lets make it a method of the class instead. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4.h

[Mesa-dev] [PATCH 08/78] i965/nir/vec4: Add setup for system values

From: Alejandro Piñeiro Similar to other variable setups, system values will initialize the corresponding register inside a 'nir_system_values' map, which will then be queried later when processing the different system value intrinsics for the appropriate register. Bugzilla: https://bugs.freedes

[Mesa-dev] [PATCH 10/78] i965/nir: Move brw_type_for_nir_type() to brw_nir to allow reuse

Upcoming NIR->vec4 pass can benefit from this method, so lets move it up. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 18 -- src/mesa/drivers/dri/i965/brw_nir.c | 18 ++ src/mesa/drivers/dri/i965/

[Mesa-dev] [PATCH 06/78] i965/nir/vec4: Add setup of uniform variables

From: Iago Toral Quiroga This is based on similar code existing in vec4_visitor. It builds the uniform register file iterating through each uniform variable. It also stores the index of each register at the corresponding offset in a map. This map will later be used by load_uniform intrinsic instr

[Mesa-dev] [PATCH 07/78] i965/vec4: Overload make_reg_for_system_value() to allow reuse in NIR->vec4 pass

From: Alejandro Piñeiro The new virtual method is more flexible, it has a signature: dst_reg *make_reg_for_system_value(int location, const glsl_type *type); so the current method will be chained through this one. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drive

[Mesa-dev] [PATCH 13/78] i965/nir/vec4: Implement conditional statements (nir_cf_node_if)

From: Iago Toral Quiroga The same we do in the FS NIR backend, only that here we need to consider the number of components in the condition and adjust the swizzle accordingly. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 23 ++

[Mesa-dev] [PATCH 14/78] i965/nir/vec4: Implement loop statements (nir_cf_node_loop)

This is taken as-is from fs_nir. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_ni

[Mesa-dev] [PATCH 17/78] i965/nir/vec4: Implement intrinsics that load system values

From: Alejandro Piñeiro These include: nir_intrinsic_load_vertex_id_zero_base nir_intrinsic_load_base_vertex nir_intrinsic_load_instance_id The source register is fetched from the nir_system_values map initialized during nir_setup_system_values stage. Bugzilla: https://bugs.freedesktop.org/sho

[Mesa-dev] [PATCH 05/78] i965/nir/vec4: Add setup of output variables in NIR->vec4 pass

This implementation sets up a map of output variable offsets to output indexes and types. This map will then be queried when processing store_output intrinsic operations, to use it as an index into the output_reg array where the output registers are stored. The original type of the variable is als

[Mesa-dev] [PATCH 16/78] i965/nir/vec4: Implement store_output intrinsic

The index into the output_reg array where to store the destination register is fetched from the nir_outputs map built during nir_setup_outputs stage. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 17 +++-- 1 file changed,

[Mesa-dev] [PATCH 11/78] i965/vec4: Add auxiliary func to build a writemask from a component size

New method brw_writemask_for_size() will return a writemask with the first 'size' components activated. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_reg.h | 9 + 1 file changed, 9 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_

[Mesa-dev] [PATCH 15/78] i965/nir/vec4: Implement load_input intrinsic

The source register is fetched from the nir_inputs map built during nir_setup_inputs stage. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 20 ++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/src/mes

[Mesa-dev] [PATCH 18/78] i965: Take is_scalar_shader_stage() method out to allow reuse

This patch makes public the is_scalar_shader_stage() method in brw_shader, and renames it to brw_compiler_is_scalar_shader_stage(). The plan is to later reuse it in brw_nir, to enable/disable optimization passes depending on the type of shader stage. The new method accepts a brw_compiler instead

[Mesa-dev] [PATCH 09/78] i965/nir/vec4: Add shader function implementation

It basically allocates registers local to a function in a nir_locals map, then emits all its control-flow blocks. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4.h | 1 + src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 12 +++- 2 fil

[Mesa-dev] [PATCH 19/78] nir/nir_lower_io: Add vec4 support

From: Iago Toral Quiroga The current implementation operates in scalar mode only, so add a vec4 mode where types are padded to vec4 sizes. This will be useful in the i965 driver for its vec4 nir backend (and possbly other drivers that have vec4-based shaders). Bugzilla: https://bugs.freedesktop

[Mesa-dev] [PATCH 12/78] i965/nir/vec4: Add nir_get_dst() and nir_get_src() methods

From: Samuel Iglesias Gonsalvez These methods are essential for the implementation of the NIR->vec4 pass. They work similar to their fs_nir counter-parts. When processing instructions, these methods are invoked to resolve the brw registers (source or destination) corresponding to the NIR sources

[Mesa-dev] [PATCH 21/78] i965/nir/vec4: Implement atomic counter intrinsics (read, inc and dec)

From: Alejandro Piñeiro The implementation is based on its fs_nir counterpart. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 24 ++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/src/mesa/drive

[Mesa-dev] [PATCH 24/78] i965/nir: Disable alu_to_scalar pass on non-scalar shaders

From: Alejandro Piñeiro Disables nir_lower_alu_to_scalar when the shader stage being processed work on vec4 vectors, like the upcoming NIR->vec4 backend. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_nir.c | 16 ++-- 1 file changed, 1

[Mesa-dev] [PATCH 22/78] i965/nir/vec4: Implement loading values from an UBO

From: Antia Puentes Based on the vec4_visitor IR implementation for the ir_binop_load_ubo operation. Notice that unlike the vec4_visitor IR, adding the !=0 comparison for UBO bools is not needed here because that comparison is already added by the nir_visitor when processing the ir_binop_load_ubo

[Mesa-dev] [PATCH 20/78] i965/nir/vec4: Implement load_uniform intrinsic

From: Iago Toral Quiroga For the indirect case we need to take the index delivered by NIR and compute the parent uniform that we are accessing (the one that we uploaded to a surface) and the constant offset into that surface. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/

[Mesa-dev] [PATCH 29/78] i965/nir/vec4: Implement multiplication

From: Antia Puentes Implementation based on the vec4_visitor IR implementation for the operations ir_binop_mul and ir_binop_imul_high. Adds NIR ALU operations: * nir_op_fmul * nir_op_imul * nir_op_imul_high * nir_op_umul_high Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89

[Mesa-dev] [PATCH 23/78] i965/nir/vec4: Prepare source and destination registers for ALU operations

From: Antia Puentes This patch resolves and initializes the destination and the source registers that are common to most ALU operations. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 19 ++- 1 file changed, 18 inser

[Mesa-dev] [PATCH 26/78] i965/nir/vec4: Lower "vecN" instructions and mark them unreachable

From: Antia Puentes This enables NIR pass "lower_vec_to_movs" on shaders that work on vec4. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_nir.c| 5 + src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 5 + 2 files changed, 10 insertions

[Mesa-dev] [PATCH 38/78] i965/nir/vec4: Implement non-vector comparison ops

From: Antia Puentes Adds NIR ALU operations: * nir_op_flt * nir_op_ilt * nir_op_ult * nir_op_fge * nir_op_ige * nir_op_uge * nir_op_feq * nir_op_ieq * nir_op_fne * nir_op_ine Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 28/78] i965/nir/vec4: Implement the addition operation

From: Antia Puentes Adds NIR ALU operations: * nir_op_fadd * nir_op_iadd Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src

[Mesa-dev] [PATCH 27/78] i965/nir/vec4: Implement int<->float format conversion ops

From: Antia Puentes Adds NIR ALU operations: * nir_op_f2i * nir_op_f2u * nir_op_i2f * nir_op_u2f Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/mesa/driv

[Mesa-dev] [PATCH 34/78] i965/vec4: Return the emitted instruction in emit_minmax()

From: Antia Puentes Needed in the NIR backend to set the "saturate" value of the instruction. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4.h | 4 ++-- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 4 +++- 2 files changed, 5 ins

[Mesa-dev] [PATCH 31/78] i965/nir/vec4: Implement more math operations

From: Antia Puentes Adds NIR ALU operations: * nir_op_frcp * nir_op_fexp2 * nir_op_flog2 * nir_op_fexp * nir_op_flog * nir_op_fsin * nir_op_fcos * nir_op_idiv * nir_op_udiv * nir_op_umod * nir_op_ldexp * nir_op_fsqrt * nir_op_frsq * nir_op_fpow Bugzilla:

[Mesa-dev] [PATCH 25/78] i965/nir/vec4: Implement single-element "mov" operations

From: Antia Puentes Adds NIR ALU operations: * nir_op_imov * nir_op_fmov Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 13 + 1 file changed, 13 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cp

[Mesa-dev] [PATCH 30/78] i965/vec4: Return the last emitted instruction in emit_math()

From: Antia Puentes Needed in the NIR backend to set the "saturate" value of the instruction. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4.h | 5 +++-- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 6 -- 2 files changed, 7

[Mesa-dev] [PATCH 33/78] i965/nir/vec4: Implement float-related functions

From: Antia Puentes Adds NIR ALU operations: * nir_op_ftrunc * nir_op_fceil * nir_op_ffloor * nir_op_ffrac * nir_op_fround_even Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 40 ++ 1 file

[Mesa-dev] [PATCH 49/78] i965/nir/vec4: Implement floating-point fused multiply-add

From: Antia Puentes Adds NIR ALU operation: * nir_op_ffma Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 9 + 1 file changed, 9 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dr

[Mesa-dev] [PATCH 42/78] i965/nir/vec4: Implement logical operators

From: Antia Puentes Adds NIR ALU operations: * nir_op_inot * nir_op_ixor * nir_op_ior * nir_op_iand Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 16 1 file changed, 16 insertions(+) diff --git a/src/m

[Mesa-dev] [PATCH 37/78] i965/nir: Add utility method for comparisons

From: Antia Puentes This method returns the brw_conditional_mod value used when emitting comparative ALU operations. It could be moved to brw_nir in the future to reuse it in fs_nir backend. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir

[Mesa-dev] [PATCH 52/78] i965/nir/vec4: Implement conditional select

From: Antia Puentes Adds NIR ALU operations: * nir_op_bcsel Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri

[Mesa-dev] [PATCH 40/78] i965/nir/vec4: Implement equality ops on vectors

From: Antia Puentes Adds NIR ALU operations: * nir_op_ball_fequal2 * nir_op_ball_iequal2 * nir_op_ball_fequal3 * nir_op_ball_iequal3 * nir_op_ball_fequal4 * nir_op_ball_iequal4 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_

[Mesa-dev] [PATCH 36/78] i965/nir/vec4: Derivatives are not allowed in VS

From: Antia Puentes Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 8 1 file changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 65c0386..0743

[Mesa-dev] [PATCH 44/78] i965/nir/vec4: "noise" ops should already be lowered

From: Antia Puentes Marked them as unreachable. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 18 ++ 1 file changed, 18 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/

[Mesa-dev] [PATCH 45/78] i965/nir/vec4: Implement pack/unpack operations

From: Antia Puentes * Lowered floating-point pack and unpack operations are not valid in VS. * Pack and unpack 2x16 operations should be handled by lower_packing_builtins. * Adds NIR ALU operations: * nir_op_pack_half_2x16 * nir_op_unpack_half_2x16 * nir_op_unpack_unorm_4x8 * nir_op

[Mesa-dev] [PATCH 32/78] i965/nir/vec4: Implement carry/borrow for addition/subtraction

From: Antia Puentes Adds NIR ALU operations: * nir_op_uadd_carry * nir_op_usub_borrow Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 16 1 file changed, 16 insertions(+) diff --git a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 39/78] i965/nir/vec4: Add swizzle utility method for vector ops

From: Antia Puentes For operations that have a predefined operand size > 0, defined in glsl/nir/nir_opcodes.c, NIR returns a swizzle containing zeros in the components from outside the source vector. However, the driver expects those components to have a swizzle value equal to the swizzle of the

[Mesa-dev] [PATCH 41/78] i965/nir/vec4: Implement non-equality ops on vectors

From: Antia Puentes Adds NIR ALU operations: * nir_op_bany_fnequal2 * nir_op_bany_inequal2 * nir_op_bany_fnequal3 * nir_op_bany_inequal3 * nir_op_bany_fnequal4 * nir_op_bany_inequal4 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw

[Mesa-dev] [PATCH 46/78] i965/nir/vec4: Implement bit operations

From: Antia Puentes Same implementation than the IR case. Adds NIR ALU operations: * nir_op_bitfield_reverse * nir_op_bit_count * nir_op_ufind_msb * nir_op_ifind_msb * nir_op_find_lsb * nir_op_ubitfield_extract * nir_op_ibitfield_extract * nir_op_bfm * nir_op_bfi *

[Mesa-dev] [PATCH 35/78] i965/nir/vec4: Implement min/max operations

From: Antia Puentes Adds NIR ALU operations: * nir_op_fmin * nir_op_imin * nir_op_umin * nir_op_fmax * nir_op_imax * nir_op_umax Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 14 ++ 1 file changed, 14

[Mesa-dev] [PATCH 53/78] i965/nir/vec4: Implement the dot product operation

From: Antia Puentes Adds NIR ALU operations: * nir_op_fdot2 * nir_op_fdot3 * nir_op_fdot4 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 15 +++ 1 file changed, 15 insertions(+) diff --git a/src/mesa/drivers/dr

[Mesa-dev] [PATCH 54/78] i965/nir/vec4: Implement vector "any" operation

From: Antia Puentes Adds NIR ALU operations: * nir_op_bany2 * nir_op_bany3 * nir_op_bany4 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 12 1 file changed, 12 insertions(+) diff --git a/src/mesa/drivers/dri/i

[Mesa-dev] [PATCH 48/78] i965/nir/vec4: Implement "shift" operations

From: Antia Puentes Adds NIR ALU operations: * nir_op_ishl * nir_op_ishr * nir_op_ushr Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 12 1 file changed, 12 insertions(+) diff --git a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 51/78] i965/nir/vec4: Implement linear interpolation

From: Antia Puentes Adds NIR ALU operation: * nir_op_flrp Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 5 + 1 file changed, 5 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i9

[Mesa-dev] [PATCH 55/78] i965/nir/vec4: Mark as unreachable ops that should be already lowered

From: Antia Puentes NIR ALU operations: * nir_op_fabs * nir_op_iabs * nir_op_fneg * nir_op_ineg * nir_op_fsat should be lowered by lower_source mods * nir_op_fdiv should be lowered in the compiler by DIV_TO_MUL_RCP. * nir_op_fmod should be lowered in

[Mesa-dev] [PATCH 58/78] i965/vec4: Move is_high_sample() method to vec4_visitor class

The is_high_sample() method is currently accessible only in the implementation of vec4_visitor. Since we need to reuse it in the upcoming NIR->vec4 pass, lets make it a method of the class instead. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_ve

[Mesa-dev] [PATCH 47/78] i965/nir/vec4: Implement the "sign" operation

From: Antia Puentes Follows the vec4_visitor IR implementation but sets the saturate value in addition. Adds NIR ALU operations: * nir_op_fsign * nir_op_isign Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 33

[Mesa-dev] [PATCH 43/78] i965/nir/vec4: Implement "bool<->int, float" format conversion

From: Antia Puentes Used the same implementation than the vec4_visitor NIR. Adds NIR ALU operations: * nir_op_b2i * nir_op_b2f * nir_op_f2b * nir_op_i2b Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 19

[Mesa-dev] [PATCH 56/78] i965/nir/vec4: Implement nir_emit_jump

This implementation is taken as-is from fs_nir. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/dr

[Mesa-dev] [PATCH 50/78] i965/vec4: Return the emitted instruction in emit_lrp()

From: Antia Puentes Needed in the NIR backend to set the "saturate" value of the instruction. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4.h | 4 ++-- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 8 2 files changed, 6

[Mesa-dev] [PATCH 57/78] i965/nir: Add new utility method brw_glsl_base_type_for_nir_type()

This method returns the glsl_base_type corresponding to a nir_alu_type. It will factorize code currently present in fs_nir, that can be reused in vec4_nir on its upcoming emit_texture support. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_fs_nir.cp

[Mesa-dev] [PATCH 63/78] i965/nir/vec4: Implement loading of nir_tex_src_comparitor

From: Alejandro Piñeiro Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_ve

[Mesa-dev] [PATCH 69/78] i965/nir/vec4: Implement nir_tex_src_sampler_offset tex source

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 25 +++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index

[Mesa-dev] [PATCH 60/78] i965/nir/vec4: Add nir_swizzle_result() method to vec4_visitor

This is the NIR->vec4 version of vec4_visitor::swizzle_result(). It is essentially the same code except that we also pass the destination register as argument, so that the result is MOVed to that register instead of to vec4_visitor::result, which is what vec4_visitor::swizzle_result() does and woul

[Mesa-dev] [PATCH 61/78] i965/nir/vec4: Add skeleton implementation of nir_emit_texture()

From: Alejandro Piñeiro This sets up the basic structure and placeholders for the implementation of texture operations, which will be added incrementally in subsequent patches. Apart from helping split the texture support into smaller patches, this patch is useful to get a simplified picture of

[Mesa-dev] [PATCH 68/78] i965/vec4: Change vec4_visitor::emit_mcs_fetch() method to allow reuse

This patch changes the signature of emit_mcs_fetch() to accept lower level arguments. The purpose is to reuse it in the upcoming NIR->vec4 pass. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4.h | 3 ++- src/mesa/drivers/dri/i965/brw_

[Mesa-dev] [PATCH 62/78] i965/vec4: Add a new dst_reg constructor accepting a brw_reg_type

From: Alejandro Piñeiro This is useful for the upcoming texture support in NIR->vec4 pass, as we found several cases where the brw_type is available, but not the glsl_type. Without this new constructor, the alternative would be: dst_reg reg(MRF, ) reg.type = reg.writemask = But adding a new c

[Mesa-dev] [PATCH 66/78] i965/nir/vec4: Implement nir_tex_src_ddx and nir_tex_src_ddy tex sources

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 0f54858..5a1d494 1006

[Mesa-dev] [PATCH 65/78] i965/nir/vec4: Setup LOD source register

From: Alejandro Piñeiro Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4

[Mesa-dev] [PATCH 67/78] i965/nir/vec4: Implement nir_tex_src_offset tex source

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 5a1d494..fa3f187 100644

[Mesa-dev] [PATCH 70/78] i965/nir/vec4: Implement nir_tex_src_ms_index tex source

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index e91e39a..

[Mesa-dev] [PATCH 75/78] i965/nir/vec4: Implement nir_texop_txd texture op

The code has been taken almost as-is from vec4_visitor. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 22 +- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp

[Mesa-dev] [PATCH 73/78] i965/nir/vec4: Implement nir_texop_txf texture op

From: Alejandro Piñeiro The code has been taken as-is from vec4_visitor. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp

[Mesa-dev] [PATCH 64/78] i965/nir/vec4: Implement loading of nir_tex_src_coord

From: Alejandro Piñeiro Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 29 +++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dr

[Mesa-dev] [PATCH 72/78] i965/nir/vec4: Implement nir_texop_txs and nir_texop_query_levels texture ops

The implementation is taken as-is from vec4_visitor. It is similar for both operations, so it makes sense to group them together. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 14 +- 1 file changed, 13 insertions(+), 1 d

[Mesa-dev] [PATCH 71/78] i965/nir/vec4: Implement nir_texop_tex and nir_texop_txl texture ops

From: Alejandro Piñeiro The implementation of these two operations is very similar, so it makes sense to group them together. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 16 +++- 1 file changed, 15 insertions(+), 1 de

[Mesa-dev] [PATCH 74/78] i965/nir/vec4: Implement nir_texop_txf_ms texture op

The code has been taken from vec4_visitor with minimum modifications. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_ni

[Mesa-dev] [PATCH 78/78] nir: Fix output swizzle in get_mul_for_src

From: Samuel Iglesias Gonsalvez Avoid copying an overwritten swizzle, use the original values. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 Signed-off-by: Samuel Iglesias Gonsalvez --- src/glsl/nir/nir_opt_peephole_ffma.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-

[Mesa-dev] [PATCH 76/78] i965/vec4: Change vec4_visitor::gather_channel() method to allow reuse

This patch changes the signature of gather_channel() to accept the gather component directly instead of fetching it internally from ir_texture. This will allow reuse in the upcoming NIR->vec4 pass. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4

[Mesa-dev] [PATCH 77/78] i965/nir/vec4: Implement nir_texop_tg4 texture op

From: Samuel Iglesias Gonsalvez The code is adapted from vec4_visitor with only minimum modifications. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 34 -- 1 file changed, 32 insertions(+), 2 deletions(-

[Mesa-dev] [PATCH 59/78] i965/nir/vec4: Add utility method shader_opcode_for_nir_opcode()

This is a helper method that returns a shader instruction opcode from the corresponding NIR texture opcode. It will be used to keep code in nir_emit_texture() clean. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89580 --- src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 39 ++

Re: [Mesa-dev] [PATCH v4 3/6] mesa/es3.1: enable GL_ARB_texture_multisample for GLES 3.1

> -Original Message- > From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On > Behalf Of Ilia Mirkin > Sent: Thursday, June 25, 2015 10:22 PM > To: Marta Lofstedt > Cc: mesa-dev@lists.freedesktop.org > Subject: Re: [Mesa-dev] [PATCH v4 3/6] mesa/es3.1: enable > GL_ARB_texture_

Re: [Mesa-dev] [PATCH v4 3/6] mesa/es3.1: enable GL_ARB_texture_multisample for GLES 3.1

On 06/26/2015 01:06 AM, Ilia Mirkin wrote: On Thu, Jun 25, 2015 at 4:22 PM, Ilia Mirkin wrote: On Thu, Jun 25, 2015 at 5:08 AM, Marta Lofstedt wrote: From: Marta Lofstedt v4 : only expose GL_ARB_texture_multisample enums for gles 3.1 and desktop GL. I was suspicious of this logic. Based

Re: [Mesa-dev] [PATCH 3/6] i965: Enable hardware-generated binding tables on render path.

On Fri, Jun 26, 2015 at 08:51:59AM +0300, Abdiel Janulgue wrote: > This patch implements the binding table enable command which is also > used to allocate a binding table pool where where hardware-generated > binding table entries are flushed into. Each binding table offset in > the binding table p

Re: [Mesa-dev] [PATCH] radeonsi: add support for geometry shader invocations.

Reviewed-by: Marek Olšák Marek On Thu, Jun 25, 2015 at 10:26 PM, Dave Airlie wrote: > From: Dave Airlie > > Signed-off-by: Dave Airlie > --- > src/gallium/drivers/radeonsi/si_shader.c| 5 + > src/gallium/drivers/radeonsi/si_shader.h| 1 + > src/gallium/drivers/radeonsi/si

Re: [Mesa-dev] [PATCH] gallium/hud: prevent NULL pointer dereference with pipe_query functions

Reviewed-by: Marek Olšák Marek On Wed, Jun 24, 2015 at 9:26 PM, Samuel Pitoiset wrote: > The HUD doesn't check if query_create() fails and it calls other > pipe_query functions with NULL pointer instead of a valid query object. > > Signed-off-by: Samuel Pitoiset > --- > src/gallium/auxiliary/

[Mesa-dev] [PATCH] st/mesa. fix crash when glBlitFramebuffer is the first function called

From: Marek Olšák No states are initialized at that point yet. Cc: 10.5 10.6 --- src/mesa/state_tracker/st_atom_constbuf.c | 14 -- src/mesa/state_tracker/st_atom_sampler.c | 30 +- src/mesa/state_tracker/st_atom_shader.c | 8 ++-- src/mesa/state

Re: [Mesa-dev] Early calls to st_validate_state

I think the best way is not to do anything if one of the shaders is NULL. Just like my patch that I just sent. Marek On Fri, Jun 26, 2015 at 3:04 AM, Ilia Mirkin wrote: > Hello, > > A user reported a crash in wine in finalize_textures (called via > st_validate_state). In this particular case it

Re: [Mesa-dev] Early calls to st_validate_state

On a different note, finalize_textures only finalizes fragment shader textures and ignores other stages, which means that either other stages have unfinalized textures (unlikely) or finalize_textures is useless. Marek On Fri, Jun 26, 2015 at 11:02 AM, Marek Olšák wrote: > I think the best way is

Re: [Mesa-dev] [PATCH v2] glsls: Modify exec_list to avoid strict-aliasing violations

On Thu, Jun 25, 2015 at 1:48 AM, Davin McCall wrote: > This is an alternative to my earlier patch [1] (and it is now constructed > properly using git format-patch). > > Quick background: > There is a problem in exec_list due to it directly including a trio > of 'struct exec_node *' members to impl

Re: [Mesa-dev] [PATCH 5/6] i965: Upload binding tables in hw-generated binding table format.

On 06/26/2015 10:55 AM, Chris Wilson wrote: > On Fri, Jun 26, 2015 at 08:52:01AM +0300, Abdiel Janulgue wrote: >> When hardware-generated binding tables are enabled, use the hw-generated >> binding table format when uploading binding table state. >> >> Normally, the CS will will just consume the

Re: [Mesa-dev] [PATCH v2] glsls: Modify exec_list to avoid strict-aliasing violations

On 26/06/15 11:08, Erik Faye-Lund wrote: On Thu, Jun 25, 2015 at 1:48 AM, Davin McCall wrote: This is an alternative to my earlier patch [1] (and it is now constructed properly using git format-patch). Quick background: There is a problem in exec_list due to it directly including a trio of 'st

[Mesa-dev] [PATCH] gallium/os: add os_wait_until_zero

From: Marek Olšák This will be used by radeon and amdgpu winsyses. Copied from the amdgpu winsys. --- src/gallium/auxiliary/os/os_time.c | 36 +++- src/gallium/auxiliary/os/os_time.h | 10 ++ 2 files changed, 45 insertions(+), 1 deletion(-) diff --git a/s

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