[Mesa-dev] [Bug 55998] Pretty huge slowdown in mesa 9.0

https://bugs.freedesktop.org/show_bug.cgi?id=55998 m...@manki.in changed: What|Removed |Added CC||m...@manki.in -- You are receiving this

[Mesa-dev] [PATCH 1/6] radeon/llvm: interp instructions emits native outputs

--- lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp | 30 +++ lib/Target/AMDGPU/R600Instructions.td | 25 +- lib/Target/AMDGPU/R600RegisterInfo.td | 10 + 3 files changed, 27 insertions(+), 38 deletions(-) diff --git a/lib/Target/A

[Mesa-dev] [PATCH 2/6] radeon/llvm: Add super reg to reserved reg list

--- lib/Target/AMDGPU/R600ISelLowering.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLowering.cpp index a7cb010..094d920 100644 --- a/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/lib/Target/AMDGPU/R600ISelLowering.cpp

[Mesa-dev] [PATCH 3/6] radeon/llvm: Remove input.face and input.position intrinsics

--- lib/Target/AMDGPU/R600ISelLowering.cpp | 35 -- lib/Target/AMDGPU/R600ISelLowering.h | 1 - lib/Target/AMDGPU/R600Intrinsics.td| 4 3 files changed, 40 deletions(-) diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLo

[Mesa-dev] [PATCH 4/6] radeon/llvm: add support for vector setCC

--- lib/Target/AMDGPU/R600ISelLowering.cpp | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLowering.cpp index 76cabae..d0711b8 100644 --- a/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/lib/Target/AMDGPU/R

[Mesa-dev] [PATCH 5/6] radeon/llvm: turn select into select_cc

--- lib/Target/AMDGPU/R600ISelLowering.cpp | 16 lib/Target/AMDGPU/R600ISelLowering.h | 1 + 2 files changed, 17 insertions(+) diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLowering.cpp index d0711b8..38d68f4 100644 --- a/lib/Target/AMDGPU/R6

[Mesa-dev] [PATCH 6/6] radeon/llvm: Cayman uses vector instruction for SIN/COS/RECIP_CLAMPED_RECIPSQRT_IEEE

--- lib/Target/AMDGPU/R600Instructions.td | 30 -- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/lib/Target/AMDGPU/R600Instructions.td b/lib/Target/AMDGPU/R600Instructions.td index b97b094..472538e 100644 --- a/lib/Target/AMDGPU/R600Instructions.td ++

[Mesa-dev] Mesa-9.0: generate_builtins.py hangs and uses 100% CPU when generating from *.glsl files

Hi, i try to (cross)compile Mesa-9.0. builtin_compiler is compiled for host with a second hostbuild before i build Mesa for target. if i build Mesa for target the buildprocess hangs at: python2 ./builtins/tools/generate_builtins.py /home/stephan/projects/openelec-master/build.OpenELEC-Intel.

[Mesa-dev] [PATCH] i965/vs: Fix debug dumping of VS push constants.

While copying the values into the batch space, we advance the param pointer. The debug code then tries to iterate over all the uploaded values, starting at param...which is now the end of the uploaded data, rather than the start. This patch saves a pointer to the start of push constant space befo

[Mesa-dev] [RFC PATCH V2] i965: add ARB_vertex_type_2_10_10_10_rev support

This series adds support for ARB_vertex_type_2_10_10_10_rev on i965. Notable changes from V1: * Extra SURFACEFORMAT flags are no longer needed, so the first patch was dropped. * Spurious extra debug patches removed. * All 2_10_10_10 attributes are uploaded as UINT, and the vertex s

[Mesa-dev] [PATCH 1/6] i965: implement get_size for 2_10_10_10 formats

Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 4 1 file changed, 4 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index f5f65ca..8ffcc57 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upl

[Mesa-dev] [PATCH 2/6] i965: support 2_10_10_10 formats in get_surface_type.

Always use R10G10B10A2_UINT; Most of the other formats we'd like don't actually work on the hardware. Will emit w/a for scaling, sign recovery and BGRA swizzle in the VS. Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 18 +- 1 file changed, 17 inser

[Mesa-dev] [PATCH 3/6] i965: Generalize GL_FIXED VS w/a support

Next few patches build on this to add other workarounds for packed formats. Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 14 +++--- src/mesa/drivers/dri/i965/brw_vs.c | 9 + src/mesa/drivers/dri/i965/brw_vs.h | 14 +

[Mesa-dev] [PATCH 4/6] i965: set attribute w/a bits for packed formats

Flag the need for various workarounds to be applied by the vertex shader. Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_vs.c | 30 ++ 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/

[Mesa-dev] [PATCH 5/6] i965: emit w/a for packed attribute formats in VS

Implements BGRA swizzle, sign recovery, and normalization as required by ARB_vertex_type_10_10_10_2_rev. This patch only adds the support to the "old" VS backend; this is what is tested by the piglit tests. Port to the new VS backend is still to come. Normalization is sloppy, and will be revisite

[Mesa-dev] [PATCH 6/6] i965: enable ARB_vertex_type_2_10_10_10_rev

Enabled on Gen4+. Signed-off-by: Chris Forbes --- docs/GL3.txt | 2 +- src/mesa/drivers/dri/intel/intel_extensions.c | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/docs/GL3.txt b/docs/GL3.txt index 876165f..6e66e55 100644 --- a/docs/GL3.tx