[Mesa-dev] [PATCH 3/6] radeon/llvm: Remove input.face and input.position intrinsics

[Vincent Lejeune]

---
 lib/Target/AMDGPU/R600ISelLowering.cpp | 35 ----------------------------------
 lib/Target/AMDGPU/R600ISelLowering.h   |  1 -
 lib/Target/AMDGPU/R600Intrinsics.td    |  4 ----
 3 files changed, 40 deletions(-)

diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp 
b/lib/Target/AMDGPU/R600ISelLowering.cpp
index 094d920..76cabae 100644
--- a/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -357,20 +357,6 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, 
SelectionDAG &DAG) const
       return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
           DL, VT, FullVector, DAG.getConstant(slot % 4, MVT::i32));
     }
-    case AMDGPUIntrinsic::R600_load_input_position: {
-      unsigned slot = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
-      unsigned RegIndex = AMDGPU::R600_TReg32RegClass.getRegister(slot);
-      SDValue Reg = CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
-           RegIndex, MVT::f32);
-      if ((slot % 4) == 3) {
-        return DAG.getNode(ISD::FDIV,
-            DL, VT,
-            DAG.getConstantFP(1.0f, MVT::f32),
-            Reg);
-      } else {
-        return Reg;
-      }
-    }
 
     case r600_read_ngroups_x:
       return LowerImplicitParameter(DAG, VT, DL, 0);
@@ -424,30 +410,9 @@ void R600TargetLowering::ReplaceNodeResults(SDNode *N,
   switch (N->getOpcode()) {
   default: return;
   case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), 
DAG));
-  case ISD::INTRINSIC_WO_CHAIN:
-    {
-      unsigned IntrinsicID =
-          cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
-      if (IntrinsicID == AMDGPUIntrinsic::R600_load_input_face) {
-        Results.push_back(LowerInputFace(N, DAG));
-      } else {
-        return;
-      }
-    }
   }
 }
 
-SDValue R600TargetLowering::LowerInputFace(SDNode* Op, SelectionDAG &DAG) const
-{
-  unsigned slot = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
-  unsigned RegIndex = AMDGPU::R600_TReg32RegClass.getRegister(slot);
-  SDValue Reg = CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
-      RegIndex, MVT::f32);
-  return DAG.getNode(ISD::SETCC, Op->getDebugLoc(), MVT::i1,
-      Reg, DAG.getConstantFP(0.0f, MVT::f32),
-      DAG.getCondCode(ISD::SETUGT));
-}
-
 SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const
 {
   return DAG.getNode(
diff --git a/lib/Target/AMDGPU/R600ISelLowering.h 
b/lib/Target/AMDGPU/R600ISelLowering.h
index 8bd4859..fd32f1b 100644
--- a/lib/Target/AMDGPU/R600ISelLowering.h
+++ b/lib/Target/AMDGPU/R600ISelLowering.h
@@ -59,7 +59,6 @@ private:
 
   SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
-  SDValue LowerInputFace(SDNode *Op, SelectionDAG &DAG) const;
   SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFPOW(SDValue Op, SelectionDAG &DAG) const;
   
diff --git a/lib/Target/AMDGPU/R600Intrinsics.td 
b/lib/Target/AMDGPU/R600Intrinsics.td
index 9c81310..d661366 100644
--- a/lib/Target/AMDGPU/R600Intrinsics.td
+++ b/lib/Target/AMDGPU/R600Intrinsics.td
@@ -19,8 +19,4 @@ let TargetPrefix = "R600", isTarget = 1 in {
     Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrReadMem]>;
   def int_R600_load_input_linear :
     Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrReadMem]>;
-  def int_R600_load_input_position :
-    Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrReadMem]>;
-  def int_R600_load_input_face :
-    Intrinsic<[llvm_i1_ty], [llvm_i32_ty], [IntrReadMem]>;
 }
-- 
1.7.11.7

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