---
lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp | 30 +++++++++++----------------
lib/Target/AMDGPU/R600Instructions.td | 25 +++++-----------------
lib/Target/AMDGPU/R600RegisterInfo.td | 10 +++++++++
3 files changed, 27 insertions(+), 38 deletions(-)
diff --git a/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
b/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
index fabdb4d..f9fd65d 100644
--- a/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
+++ b/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
@@ -95,8 +95,9 @@ bool
R600ExpandSpecialInstrsPass::ExpandInputPerspective(MachineInstr &MI)
for (unsigned i = 0; i < 8; i++) {
unsigned IJIndex = AMDGPU::R600_TReg32RegClass.getRegister(
2 * IJIndexBase + ((i + 1) % 2));
- unsigned ReadReg = AMDGPU::R600_TReg32RegClass.getRegister(
- 4 * MI.getOperand(2).getImm());
+ unsigned ReadReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
+ MI.getOperand(2).getImm());
+
unsigned Sel;
switch (i % 4) {
@@ -109,16 +110,11 @@ bool
R600ExpandSpecialInstrsPass::ExpandInputPerspective(MachineInstr &MI)
unsigned Res = TRI.getSubReg(DstReg, Sel);
- const MCInstrDesc &Opcode = (i < 4)?
- TII->get(AMDGPU::INTERP_ZW):
- TII->get(AMDGPU::INTERP_XY);
+ unsigned Opcode = (i < 4)?AMDGPU::INTERP_ZW:AMDGPU::INTERP_XY;
- MachineInstr *NewMI = BuildMI(*(MI.getParent()),
- I, MI.getParent()->findDebugLoc(I),
- Opcode, Res)
- .addReg(IJIndex)
- .addReg(ReadReg)
- .addImm(0);
+ MachineBasicBlock &MBB = *(MI.getParent());
+ MachineInstr *NewMI =
+ TII->buildDefaultInstruction(MBB, I, Opcode, Res, IJIndex, ReadReg);
if (!(i> 1 && i < 6)) {
TII->addFlag(NewMI, 0, MO_FLAG_MASK);
@@ -143,8 +139,8 @@ bool
R600ExpandSpecialInstrsPass::ExpandInputConstant(MachineInstr &MI)
unsigned DstReg = MI.getOperand(0).getReg();
for (unsigned i = 0; i < 4; i++) {
- unsigned ReadReg = AMDGPU::R600_TReg32RegClass.getRegister(
- 4 * MI.getOperand(1).getImm() + i);
+ unsigned ReadReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
+ MI.getOperand(1).getImm());
unsigned Sel;
switch (i % 4) {
@@ -157,11 +153,9 @@ bool
R600ExpandSpecialInstrsPass::ExpandInputConstant(MachineInstr &MI)
unsigned Res = TRI.getSubReg(DstReg, Sel);
- MachineInstr *NewMI = BuildMI(*(MI.getParent()),
- I, MI.getParent()->findDebugLoc(I),
- TII->get(AMDGPU::INTERP_LOAD_P0), Res)
- .addReg(ReadReg)
- .addImm(0);
+ MachineBasicBlock &MBB = *(MI.getParent());
+ MachineInstr *NewMI = TII->buildDefaultInstruction(
+ MBB, I, AMDGPU::INTERP_LOAD_P0, Res, ReadReg);
if (i % 4 != 3)
TII->addFlag(NewMI, 0, MO_FLAG_NOT_LAST);
diff --git a/lib/Target/AMDGPU/R600Instructions.td
b/lib/Target/AMDGPU/R600Instructions.td
index 7cc74e8..b97b094 100644
--- a/lib/Target/AMDGPU/R600Instructions.td
+++ b/lib/Target/AMDGPU/R600Instructions.td
@@ -444,32 +444,17 @@ def input_constant : AMDGPUShaderInst <
-def INTERP_XY : InstR600 <0xD6,
- (outs R600_Reg32:$dst),
- (ins R600_Reg32:$src0, R600_Reg32:$src1, i32imm:$flags),
- "INTERP_XY dst",
- [], AnyALU>
+def INTERP_XY : R600_2OP <0xD6, "INTERP_XY", []>
{
- let FlagOperandIdx = 3;
+ let bank_swizzle = 5;
}
-def INTERP_ZW : InstR600 <0xD7,
- (outs R600_Reg32:$dst),
- (ins R600_Reg32:$src0, R600_Reg32:$src1, i32imm:$flags),
- "INTERP_ZW dst",
- [], AnyALU>
+def INTERP_ZW : R600_2OP <0xD7, "INTERP_ZW", []>
{
- let FlagOperandIdx = 3;
+ let bank_swizzle = 5;
}
-def INTERP_LOAD_P0 : InstR600 <0xE0,
- (outs R600_Reg32:$dst),
- (ins R600_Reg32:$src, i32imm:$flags),
- "INTERP_LOAD_P0 dst",
- [], AnyALU>
-{
- let FlagOperandIdx = 2;
-}
+def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
let Predicates = [isR600toCayman] in {
diff --git a/lib/Target/AMDGPU/R600RegisterInfo.td
b/lib/Target/AMDGPU/R600RegisterInfo.td
index c682f2b..d3d6d25 100644
--- a/lib/Target/AMDGPU/R600RegisterInfo.td
+++ b/lib/Target/AMDGPU/R600RegisterInfo.td
@@ -41,6 +41,12 @@ foreach Index = 0-127 in {
Index>;
}
+// Array Base Register holding input in FS
+foreach Index = 448-464 in {
+ def ArrayBase#Index : R600Reg<"ARRAY_BASE", Index>;
+}
+
+
// Special Registers
def ZERO : R600Reg<"0.0", 248>;
@@ -56,6 +62,9 @@ def PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>;
def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>;
def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>;
+def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
+ (add (sequence "ArrayBase%u", 448, 464))>;
+
def R600_CReg32 : RegisterClass <"AMDGPU", [f32, i32], 32,
(add (interleave
(interleave (sequence "C%u_X", 0, 127),
@@ -83,6 +92,7 @@ def R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32,
def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
R600_TReg32,
R600_CReg32,
+ R600_ArrayBase,
ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF)>;
def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add
--
1.7.11.7
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