On 07.08.2015 00:11, Marek Olšák wrote:
> From: Marek Olšák
>
> v2: just clear the flag before the allocation
> ---
> src/gallium/drivers/radeon/r600_buffer_common.c | 3 +++
> src/gallium/drivers/radeon/r600_pipe_common.c | 1 +
> src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
> 3 fil
On 07.08.2015 00:17, Christian König wrote:
>> can we disable HDP flushes and other flushes for USWC
What other flushes are you thinking of? If you mean the mb() in the
kernel which flushes the write-combining buffers, that's also needed for
the register writes regardless of write-combining.
>>
can we disable HDP flushes and other flushes for
USWC when we don't use write
combining and CPU writes to VRAM?
Nope, write combining happens in the CPU before the write request is
send over the PCIe bus.
The HDP is a (rather small) read/write cache in GPUs memory controller
as far as I know.
From: Marek Olšák
v2: just clear the flag before the allocation
---
src/gallium/drivers/radeon/r600_buffer_common.c | 3 +++
src/gallium/drivers/radeon/r600_pipe_common.c | 1 +
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
3 files changed, 5 insertions(+)
diff --git a/src/gallium/dr
On a related note, can we disable HDP flushes and other flushes for
USWC when we don't use write
combining and CPU writes to VRAM? Maybe by adding a per-IB flag that
would instruct the
kernel to flush or not flush HDP?
Marek
On Wed, Aug 5, 2015 at 4:18 AM, Michel Dänzer wrote:
> On 03.08.2015 21
On 03.08.2015 21:36, Marek Olšák wrote:
> From: Marek Olšák
>
> ---
> src/gallium/drivers/radeon/r600_buffer_common.c | 6 --
> src/gallium/drivers/radeon/r600_pipe_common.c | 1 +
> src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
> 3 files changed, 6 insertions(+), 2 deletions(
From: Marek Olšák
---
src/gallium/drivers/radeon/r600_buffer_common.c | 6 --
src/gallium/drivers/radeon/r600_pipe_common.c | 1 +
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_buffer_co
