On Tuesday, January 16, 2018 9:48:07 PM PST Rhys Kidd wrote:
> Symbol rename from dri_* to drm_intel_* introduced a number of compatability
> defines within intel_bufmgr.h.
>
> Replace the old function with the new function, consistent with the balance
> of this file.
>
> Signed-off-by: Rhys Kidd
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_image.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 4d13e05e11f..72e408764d8 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/
On 16/01/18 17:10, Jason Ekstrand wrote:
> I'm a bit unclear here. Was ISL crashing before or was it returning
> false and anv crashing? If it was anv crashing due to an assert(ok),
> then maybe it's best to just make anv fail gracefully with
> VK_ERROR_OUT_OF_DEVICE_MEMORY. Setting size to UINT
https://bugs.freedesktop.org/show_bug.cgi?id=103538
--- Comment #7 from mais...@archlinux.us ---
This might not be a bug after all. The app destroyed the X window before
tearing down the swapchain, which is bogus, and probably where the deadlock
comes from. It stopped once it was done properly.
-
On Tue, Jan 16, 2018 at 4:30 PM, Nanley Chery wrote:
> On Tue, Jan 16, 2018 at 12:02:43PM -0800, Nanley Chery wrote:
> > On Sat, Jan 13, 2018 at 11:11:35AM -0800, Jason Ekstrand wrote:
> > > Sorry for all the list spam, but I'm sort of thinking out-loud and
> writing
> > > it on the list for all
Symbol rename from dri_* to drm_intel_* introduced a number of compatability
defines within intel_bufmgr.h.
Replace the old function with the new function, consistent with the balance
of this file.
Signed-off-by: Rhys Kidd
---
src/mesa/drivers/dri/i915/intel_regions.c | 2 +-
1 file changed, 1
On 01/17/2018 05:49 AM, Marek Olšák wrote:
On Wed, Jan 17, 2018 at 3:21 AM, Mario Kleiner
wrote:
On 01/16/2018 11:47 PM, Marek Olšák wrote:
Why?
Because the bug reports i've seen so far seem to be not caused by something
specific to the i965 implementation, but by some other client applica
---
src/mesa/vbo/vbo_exec_draw.c | 7 +++
src/mesa/vbo/vbo_save_draw.c | 7 +++
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/src/mesa/vbo/vbo_exec_draw.c b/src/mesa/vbo/vbo_exec_draw.c
index 5d1e588..68e9918 100644
--- a/src/mesa/vbo/vbo_exec_draw.c
+++ b/src/mesa/vbo/vbo
---
src/mesa/vbo/vbo_exec_draw.c | 128 +--
1 file changed, 64 insertions(+), 64 deletions(-)
diff --git a/src/mesa/vbo/vbo_exec_draw.c b/src/mesa/vbo/vbo_exec_draw.c
index 68e9918..3e1556b 100644
--- a/src/mesa/vbo/vbo_exec_draw.c
+++ b/src/mesa/vbo/vbo_ex
---
src/mesa/vbo/vbo_split_copy.c | 304 --
1 file changed, 144 insertions(+), 160 deletions(-)
diff --git a/src/mesa/vbo/vbo_split_copy.c b/src/mesa/vbo/vbo_split_copy.c
index 8e35e44..2de909f 100644
--- a/src/mesa/vbo/vbo_split_copy.c
+++ b/src/mesa/vbo/v
---
src/mesa/vbo/vbo_attrib.h | 100 +++---
1 file changed, 50 insertions(+), 50 deletions(-)
diff --git a/src/mesa/vbo/vbo_attrib.h b/src/mesa/vbo/vbo_attrib.h
index f4a3a66..fb11596 100644
--- a/src/mesa/vbo/vbo_attrib.h
+++ b/src/mesa/vbo/vbo_attrib.h
@@
Both state->prog->info.inputs_read and state->InputsBound are GLbitfield64
so it seems that the OR of those values should be of the same type.
I'm not sure this fixes any actual issues though.
---
src/mesa/program/program_parse.y | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/
---
src/mesa/vbo/vbo_exec_api.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/mesa/vbo/vbo_exec_api.c b/src/mesa/vbo/vbo_exec_api.c
index 019f986..800fac8 100644
--- a/src/mesa/vbo/vbo_exec_api.c
+++ b/src/mesa/vbo/vbo_exec_api.c
@@ -270,6 +270,7 @@ vbo_exec_copy_f
The values will never be larger than VBO_ATTRIB_MAX (currently 44).
---
src/mesa/vbo/vbo_context.h | 4 ++--
src/mesa/vbo/vbo_exec_draw.c | 2 +-
src/mesa/vbo/vbo_save_draw.c | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/mesa/vbo/vbo_context.h b/src/mesa/vbo/vbo_co
Make the code a bit more concise.
---
src/mesa/vbo/vbo_save_draw.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/src/mesa/vbo/vbo_save_draw.c b/src/mesa/vbo/vbo_save_draw.c
index c1298f9..5d299d8 100644
--- a/src/mesa/vbo/vbo_save_draw.c
+++ b/src/
---
src/mesa/vbo/vbo_exec_api.c | 197 ++--
1 file changed, 98 insertions(+), 99 deletions(-)
diff --git a/src/mesa/vbo/vbo_exec_api.c b/src/mesa/vbo/vbo_exec_api.c
index 800fac8..6f1c550 100644
--- a/src/mesa/vbo/vbo_exec_api.c
+++ b/src/mesa/vbo/vbo_exec_
---
src/mesa/vbo/vbo_context.c | 59 +++---
1 file changed, 35 insertions(+), 24 deletions(-)
diff --git a/src/mesa/vbo/vbo_context.c b/src/mesa/vbo/vbo_context.c
index a5f915d..971f298 100644
--- a/src/mesa/vbo/vbo_context.c
+++ b/src/mesa/vbo/vbo_context.
Both switch cases began with the same code.
---
src/mesa/vbo/vbo_exec_draw.c | 15 ++-
src/mesa/vbo/vbo_save_draw.c | 15 ++-
2 files changed, 12 insertions(+), 18 deletions(-)
diff --git a/src/mesa/vbo/vbo_exec_draw.c b/src/mesa/vbo/vbo_exec_draw.c
index 34cb4ff..de17322
---
src/mesa/vbo/vbo_context.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/mesa/vbo/vbo_context.c b/src/mesa/vbo/vbo_context.c
index 971f298..02989d5 100644
--- a/src/mesa/vbo/vbo_context.c
+++ b/src/mesa/vbo/vbo_context.c
@@ -25,9 +25,7 @@
*Keith Whitwell
*/
-#include "mai
The two headers already have the right extern "C" annotations.
---
src/compiler/glsl/serialize.cpp | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/compiler/glsl/serialize.cpp b/src/compiler/glsl/serialize.cpp
index 769ab56..63ce41d 100644
--- a/src/compiler/glsl/seria
To get memset() prototype.
---
src/util/u_dynarray.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/util/u_dynarray.h b/src/util/u_dynarray.h
index cc31632..dcbbc06 100644
--- a/src/util/u_dynarray.h
+++ b/src/util/u_dynarray.h
@@ -28,6 +28,7 @@
#define U_DYNARRAY_H
#include
+#includ
The function is only called from a couple places. It doesn't make
sense to have it in mtypes.h
---
src/mesa/main/mtypes.h | 17 -
src/mesa/program/program.c | 17 +
src/mesa/program/program.h | 5 +
3 files changed, 22 insertions(+), 17 deletions(-)
diff
---
src/mesa/drivers/x11/glxapi.c| 1 -
src/mesa/main/debug_output.h | 1 -
src/mesa/main/errors.h | 1 -
src/mesa/main/fbobject.h | 1 -
src/mesa/main/formatquery.h | 1 -
src/mesa/main/formats.h
Instead of indirect inclusion to get CPU_TO_LE32() macro.
---
src/util/disk_cache.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/util/disk_cache.c b/src/util/disk_cache.c
index 7ebfa8c..2884d3c 100644
--- a/src/util/disk_cache.c
+++ b/src/util/disk_cache.c
@@ -46,6 +46,7 @@
#include "u
Instead of relying on indirect inclusion of the header.
---
src/compiler/glsl/serialize.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/compiler/glsl/serialize.cpp b/src/compiler/glsl/serialize.cpp
index 57c91d9..769ab56 100644
--- a/src/compiler/glsl/serialize.cpp
+++ b/src/compiler/g
And use "" instead of <> for including Mesa headers, as we do elsewhere.
---
src/mesa/state_tracker/st_glsl_to_tgsi_temprename.cpp | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi_temprename.cpp
b/src/mesa/state_tracker/st_glsl
To get definition of unreachable() macro.
---
src/mesa/main/format_fallback.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/main/format_fallback.py b/src/mesa/main/format_fallback.py
index 2f02d0d..4a2b85c 100644
--- a/src/mesa/main/format_fallback.py
+++ b/src/mesa/main/format_fal
---
src/mesa/state_tracker/st_cb_bitmap.h| 1 -
src/mesa/state_tracker/st_cb_blit.h | 2 --
src/mesa/state_tracker/st_cb_bufferobjects.h | 1 -
src/mesa/state_tracker/st_cb_compute.h | 2 --
src/mesa/state_tracker/st_cb_drawpixels.h| 1 -
src/mesa/state_tracker/st_cb_dra
To get CPU_TO_LE32() macro.
---
src/mesa/state_tracker/st_cb_queryobj.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/state_tracker/st_cb_queryobj.c
b/src/mesa/state_tracker/st_cb_queryobj.c
index a470ff6..69e6004 100644
--- a/src/mesa/state_tracker/st_cb_queryobj.c
+++ b/src/mesa/
On Wed, Jan 17, 2018 at 3:21 AM, Mario Kleiner
wrote:
> On 01/16/2018 11:47 PM, Marek Olšák wrote:
>>
>> Why?
>
>
> Because the bug reports i've seen so far seem to be not caused by something
> specific to the i965 implementation, but by some other client application or
> compositor being incompat
Looks good.
Reviewed-by: Neha Bhende
From: Brian Paul
Sent: Friday, January 12, 2018 2:22:07 PM
To: mesa-dev@lists.freedesktop.org
Cc: Neha Bhende; Charmaine Lee
Subject: [PATCH] svga: add num-commands-per-draw HUD query
This query shows the ratio of total command
https://bugs.freedesktop.org/show_bug.cgi?id=103699
--- Comment #30 from Mario Kleiner ---
We should also get this cherry-picked into the 1.19 branch. Otherwise it might
happen that the new Mesa ships in spring distribution releases with an old 1.19
X-Server, e.g., Ubuntu 18.04-LTS.
--
You are
On 01/16/2018 11:47 PM, Marek Olšák wrote:
Why?
Because the bug reports i've seen so far seem to be not caused by
something specific to the i965 implementation, but by some other client
application or compositor being incompatible. Therefore i'd expect the
same problems in clients/compositor
---
src/amd/vulkan/radv_pipeline.c | 83 +-
src/amd/vulkan/radv_private.h | 8
2 files changed, 34 insertions(+), 57 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 9b557f9c23..2f4561d1c2 100644
--- a/s
---
src/amd/vulkan/radv_pipeline.c | 130 +++--
src/amd/vulkan/radv_private.h | 12
2 files changed, 73 insertions(+), 69 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 16dad89f4c..9d95073260 100644
--- a/
---
src/amd/vulkan/radv_pipeline.c | 115 ++---
src/amd/vulkan/radv_private.h | 10
2 files changed, 50 insertions(+), 75 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index e1d6fe159d..232c06c9a8 100644
--- a/
---
src/amd/vulkan/radv_pipeline.c | 160 -
src/amd/vulkan/radv_private.h | 2 -
2 files changed, 79 insertions(+), 83 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index bd8a2feb8c..8c5706f4b4 100644
--- a/src
---
src/amd/vulkan/radv_pipeline.c | 51 +-
src/amd/vulkan/radv_private.h | 2 --
2 files changed, 25 insertions(+), 28 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 4357669baa..a5239e7a6d 100644
--- a/src
We don't have the meta kludge with 0 viewports anymore,
so we can always enable them.
---
src/amd/vulkan/radv_cmd_buffer.c | 4 ++--
src/amd/vulkan/radv_pipeline.c | 3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_b
---
src/amd/vulkan/radv_pipeline.c | 13 ++---
src/amd/vulkan/radv_private.h | 1 -
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 2f4561d1c2..bd8a2feb8c 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++
---
src/amd/vulkan/radv_pipeline.c | 57 --
src/amd/vulkan/radv_private.h | 1 -
2 files changed, 33 insertions(+), 25 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index a5239e7a6d..639eb032bb 100644
--- a/src/
---
src/amd/vulkan/radv_pipeline.c | 78 +++---
src/amd/vulkan/radv_private.h | 8 -
2 files changed, 43 insertions(+), 43 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 639eb032bb..e1d6fe159d 100644
--- a/
---
src/amd/vulkan/radv_pipeline.c | 78 +++---
1 file changed, 43 insertions(+), 35 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index cc88a7b10e..4357669baa 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd
---
src/amd/vulkan/radv_pipeline.c | 95 ++
src/amd/vulkan/radv_private.h | 13 --
2 files changed, 58 insertions(+), 50 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 9d95073260..cc88a7b10e 100644
--- a
---
src/amd/vulkan/radv_pipeline.c | 50 +++---
src/amd/vulkan/radv_private.h | 1 -
2 files changed, 27 insertions(+), 24 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 9d6663e977..16dad89f4c 100644
--- a/src/
---
src/amd/vulkan/radv_pipeline.c | 10 +++---
src/amd/vulkan/radv_private.h | 1 -
2 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index dbe33d3cc5..b39ee4308b 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/s
---
src/amd/vulkan/radv_pipeline.c | 66 ++
src/amd/vulkan/radv_private.h | 19
2 files changed, 85 insertions(+)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 82d9546cc3..ffd5aab7f9 100644
--- a/src/amd/vu
---
src/amd/vulkan/radv_pipeline.c | 43 +-
src/amd/vulkan/radv_private.h | 1 -
2 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index b39ee4308b..be71abd858 100644
--- a/src/
The user SGPR location can change between pipelines, so we need to
emit it again to the pottentially changed SGPR index.
---
src/amd/vulkan/radv_cmd_buffer.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/
Also moved everything in a struct and then return the struct from
the helper function, so it is clear in the caller what part of the
pipeline gets modified.
---
src/amd/vulkan/radv_pipeline.c | 169 ++---
src/amd/vulkan/radv_private.h | 16 ++--
src/amd/vulkan
Which avoids setting or emitting them.
---
src/amd/vulkan/radv_cmd_buffer.c | 40 +++--
src/amd/vulkan/radv_pipeline.c | 64 +---
src/amd/vulkan/radv_private.h| 1 +
3 files changed, 65 insertions(+), 40 deletions(-)
diff --git a/src/
---
src/amd/vulkan/radv_pipeline.c | 8
src/amd/vulkan/radv_private.h | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 22dd6566a1..1eddacfe51 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/sr
We don't need the pipeline state struct anymore.
---
src/amd/vulkan/radv_pipeline.c | 48 +-
src/amd/vulkan/radv_private.h | 6 --
2 files changed, 19 insertions(+), 35 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pip
---
src/amd/vulkan/radv_pipeline.c | 117 +++--
src/amd/vulkan/radv_private.h | 8 ---
2 files changed, 55 insertions(+), 70 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 8c5706f4b4..dbe33d3cc5 100644
--- a/s
This gives about 2% performance improvement on dota2 for me.
This is mostly a mechanical copy and replacement, but at bind time
we still do:
1) Some stuff that is only based on num_samples changes.
2) Some command buffer state setting.
---
src/amd/vulkan/radv_cmd_buffer.c | 458 +
This changes emitting pipelines to pregenerate the PM$ sequences to bind the
pipeline at pipeline creation time, so we can just memcpy it in the command
buffer. This gives minor CPU improvements on dota2.
In the process I also refactored stuff to:
1) Not have all the state in the pipeline struct
---
src/amd/vulkan/radv_cmd_buffer.c | 60 ++--
src/amd/vulkan/radv_pipeline.c | 66
2 files changed, 68 insertions(+), 58 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index
On 01/16/2018 10:11 AM, Ian Romanick wrote:
> On 01/13/2018 01:47 PM, Jason Ekstrand wrote:
>> On January 12, 2018 14:56:26 "Ian Romanick" wrote:
>>
>>> From: Ian Romanick
>>>
>>> With the exception of NVIDIA hardware, these are is the values that all
>>> hardware and Gallium want. The remapping
On 01/16/2018 10:59 AM, Brian Paul wrote:
> On 01/16/2018 11:12 AM, Ian Romanick wrote:
>> On 01/15/2018 11:23 AM, Brian Paul wrote:
>>> On 01/12/2018 03:56 PM, Ian Romanick wrote:
From: Ian Romanick
With the exception of NVIDIA hardware, these are is the values that all
hardwa
From: Ian Romanick
shader-db results:
Skylake and Broadwell had similar results (Skylake shown)
total instructions in shared programs: 14526033 -> 14526021 (<.01%)
instructions in affected programs: 1450 -> 1438 (-0.83%)
helped: 12
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped s
From: Ian Romanick
Skylake, Broadwell, and Haswell had similar results. Skylake shown.
total instructions in shared programs: 14521954 -> 14521938 (<.01%)
instructions in affected programs: 8782 -> 8766 (-0.18%)
helped: 16
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel
From: Ian Romanick
v2: Rebase on almost 2 years. Require that one of the arguments to fmin
or fmax be used only once. This prevents some regressions.
shader-db results:
Skylake, Broadwell, and Haswell had similar results. Skylake shown.
total instructions in shared programs: 14526021 -> 1452
From: Ian Romanick
If both comparisons are used as sources for instructions other than the
ior, this transformation is detrimental. If the non-identical value in
both compares is constant, the fmin or fmax will be constant-folded
away, so the transformation is always a win.
shader-db results:
From: Ian Romanick
This was specifically designed to simplify 1+mix(0, a-1, condition) to
mix(1, a, condition) by pushing the 1+ inside.
Skylake, Broadwell, and Haswell had similar results. Skylake shown.
total instructions in shared programs: 14521938 -> 14521901 (<.01%)
instructions in affect
From: Ian Romanick
min(a+b, c+d) >= 0 becomes (a+b >= 0 && c+d >= 0).
No shader-db changes, but it does prevent 6 to 12 instruction
regressions in the next patch on all measured Intel platforms.
Signed-off-by: Ian Romanick
---
src/compiler/nir/nir_opt_algebraic.py | 2 ++
1 file changed, 2 in
From: Ian Romanick
Doing the same for the existing feq and fne transformations didn't help
anything in shader-db.
shader-db results:
Skylake
total instructions in shared programs: 14529598 -> 14526282 (-0.02%)
instructions in affected programs: 402420 -> 399104 (-0.82%)
helped: 2136
HURT: 131
h
From: Ian Romanick
If both comparisons are used as sources for instructions other than the
iand, this transformation is detrimental. If the non-identical value in
both compares is constant, the fmin or fmax will be constant-folded
away, so the transformation is always a win.
It is interesting t
This is the first series to resurrect some work that I started as long
as 2.5 years ago. A lot of that work produced mixed bag results, but
that was before nir_opt_algebraic.py had the "is_used_once" modifier.
Without this, the last patch was more like 50 helped / 500 hurt on most
platforms.
All
On Tuesday, January 16, 2018 4:21:57 PM PST Kenneth Graunke wrote:
> On Wednesday, January 10, 2018 11:22:39 AM PST Jason Ekstrand wrote:
> > ---
> > src/mesa/drivers/dri/i965/brw_draw.c | 41
> >
> > 1 file changed, 41 insertions(+)
> >
> > diff --git a/src/
Reviewed-by: Marek Olšák
Marek
On Thu, Jan 11, 2018 at 3:47 AM, Timothy Arceri wrote:
> Lowering these to temps makes a big mess, and results in some
> piglit test failures. Also the radeonsi backend (the only backend
> to support tess) has support for indirects so there is no need to
> lower t
https://bugs.freedesktop.org/show_bug.cgi?id=104654
--- Comment #3 from Gert Wollny ---
Now, considering that compute shaders don't use sb there are likely two issues
at hand here. Without sb AI hangs quite often for a second or so (especially
when opening the map), and it completely hung like re
For the series:
Reviewed-by: Marek Olšák
Marek
On Fri, Jan 12, 2018 at 11:21 PM, Brian Paul wrote:
> Evidently, nobody has used PIPE_DRIVER_QUERY_TYPE_FLOAT up to this
> point. Adding a driver query of this type which returns the query
> value in pipe_query_result::f resulted in garbage outpu
On Tuesday, January 16, 2018 3:15:40 PM PST Jason Ekstrand wrote:
> This makes sure we flush things out of other caches prior to using a
> surface through the render cache. Currently, this is a no-op because GL
> won't let you bind anything other than a color surface as color so it
> should never
On Tue, Jan 16, 2018 at 12:02:43PM -0800, Nanley Chery wrote:
> On Sat, Jan 13, 2018 at 11:11:35AM -0800, Jason Ekstrand wrote:
> > Sorry for all the list spam, but I'm sort of thinking out-loud and writing
> > it on the list for all to read.
> >
> > I'm thinking that what we want this list to ret
https://bugs.freedesktop.org/show_bug.cgi?id=104654
--- Comment #2 from Gert Wollny ---
Actually, the GPU lockups also happen without sb, only not to the point that
one has to kill the program. It is likely that #104665 is actually a duplicate
of this.
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Yo
On Wednesday, January 10, 2018 11:22:40 AM PST Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
On 2018-01-16 13:57:37, Kenneth Graunke wrote:
> On Tuesday, January 16, 2018 11:18:13 AM PST Emil Velikov wrote:
> > Hi all,
> >
> > As you've know the Mesa 18.0.0 release plan has been available for a while
> > on the mesa3d.org website [1].
> >
> > In case you've missed it here it is:
> >
> >
On Wednesday, January 10, 2018 11:22:39 AM PST Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_draw.c | 41
>
> 1 file changed, 41 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
> b/src/mesa/drivers/dri/i965/brw_draw.c
> inde
On Tue, Jan 16, 2018 at 11:36 AM, Robert Foss wrote:
> Supply accessor functions for most of the common gralloc_handle_t
> variables.
>
> Signed-off-by: Robert Foss
> ---
> android/gralloc_handle.h | 57
>
> 1 file changed, 57 insertions(+)
>
> d
On Wednesday, January 10, 2018 11:22:36 AM PST Jason Ekstrand wrote:
> This lets us perform render cache flushes whenever a surface goes from
> being used with one aux+format to a different aux+format.
>
> This is the "proper" fix for https://bugs.freedesktop.org/102435.
> ee57b15ec764736e2d5360be
On Wednesday, January 10, 2018 11:22:38 AM PST Jason Ekstrand wrote:
> This commit unifies the CCS_E and CCS_D cases. This should fix a couple
> of subtle issues. One is that when you use INTEL_DEBUG=norbc to disable
> CCS_E, we don't get the sRGB blending workaround. By unifying the code,
> we
On Tue, Jan 16, 2018 at 11:36 AM, Robert Foss wrote:
> This struct is used in mesa and drm_hwcomposer.
> Versions of if have been implemented in several grallocs:
> drm_gralloc, gbm_gralloc, minigbm and intel-minigbm.
>
> Other than the 1:1 move of the struct a new generic name
> has been chosen a
On Tue, Jan 16, 2018 at 11:36 AM, Robert Foss wrote:
> This struct is used in mesa and drm_hwcomposer.
> Versions of if have been implemented in several grallocs:
> drm_gralloc, gbm_gralloc, minigbm and intel-minigbm.
>
> Other than the 1:1 move of the struct a new generic name
> has been chosen a
This makes sure we flush things out of other caches prior to using a
surface through the render cache. Currently, this is a no-op because GL
won't let you bind anything other than a color surface as color so it
should never end up in the depth cache. However, this does complete the
flush/add_bo p
On Friday, November 17, 2017 2:28:47 PM PST Francisco Jerez wrote:
> A primitive counter encapsulates a scalar aggregating counter for each
> vertex stream along with a section within the primitive tally buffer
> which hasn't been read out yet. Defining this as a separate type will
> allow us to k
Acked-by: Marek Olšák
Marek
On Sun, Jan 14, 2018 at 10:59 PM, Grazvydas Ignotas wrote:
> Trivial. Found by Coccinelle.
> ---
> src/gallium/drivers/radeon/radeon_vcn_dec.c | 6 +++---
> src/mesa/drivers/dri/radeon/radeon_debug.c | 2 +-
> src/mesa/drivers/dri/radeon/radeon_state_init.c
Reviewed-by: Marek Olšák
Marek
On Fri, Jan 12, 2018 at 6:52 AM, Timothy Arceri wrote:
> I'm guessing this may have been disable because of missing
> component packing support. However recent nir linking changes
> required nir based gallium drivers to support component packing
> so this should n
https://bugs.freedesktop.org/show_bug.cgi?id=104662
--- Comment #3 from Vedran Miletić ---
(In reply to Stewart Little from comment #2)
> How do I then get steam to switch to the 4.5 OpenGL and get it as default on
> Arch Linux then? Any help would be appreciated I seriously don't know how to
> c
Why?
Marek
On Tue, Jan 16, 2018 at 5:39 AM, Mario Kleiner
wrote:
> For consistency with the i965 default of "off".
>
> Signed-off-by: Mario Kleiner
> ---
> src/gallium/auxiliary/pipe-loader/driinfo_gallium.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/a
On Tuesday, January 16, 2018 11:18:13 AM PST Emil Velikov wrote:
> Hi all,
>
> As you've know the Mesa 18.0.0 release plan has been available for a while
> on the mesa3d.org website [1].
>
> In case you've missed it here it is:
>
> Jan 19 2018 - Feature freeze/Release candidate 1
> Jan 26 2018
Ian Romanick writes:
> On 12/20/2017 11:27 AM, Francisco Jerez wrote:
>> Previously the dataflow propagation algorithm would calculate the ACP
>> live-in and -out sets in a two-pass fixed-point algorithm. The first
>> pass would update the live-out sets of all basic blocks of the program
>> base
On 12/20/2017 11:27 AM, Francisco Jerez wrote:
> Previously the dataflow propagation algorithm would calculate the ACP
> live-in and -out sets in a two-pass fixed-point algorithm. The first
> pass would update the live-out sets of all basic blocks of the program
> based on their live-in sets, whil
> On Jan 16, 2018, at 1:59 PM, Chuck Atkins wrote:
>
> Part 2 of 2 (part 1 is autoconf changes, part 2 is C++ changes)
>
> When only a single SWR architecture is being used, this allows that
> architecture to be builtin rather than as a separate libswrARCH.so that
> gets loaded via dlopen. Sin
https://bugs.freedesktop.org/show_bug.cgi?id=104665
Bug ID: 104665
Summary: r600: computer shaders break Bioshock on barts
(bisected)
Product: Mesa
Version: git
Hardware: Other
OS: All
Status: NE
cc: Dylan Baker
---
src/gallium/drivers/swr/meson.build | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/swr/meson.build
b/src/gallium/drivers/swr/meson.build
index c8c69b0..8dffb4c 100644
--- a/src/gallium/drivers/swr/meson.build
+++ b/src/gallium/drivers/swr/meson.build
We can instead just get this from st_*_program.
V2: store tokens to to st_compute_program before attempting to
write to cache (fixes crash).
Tested-by: Dieter Nützel
---
src/mesa/state_tracker/st_program.c | 8
src/mesa/state_tracker/st_shader_cache.c | 22 ---
These will be shared between the on-disk shader cache and
ARB_get_program_binary.
Tested-by: Dieter Nützel
---
src/mesa/state_tracker/st_shader_cache.c | 265 ---
src/mesa/state_tracker/st_shader_cache.h | 8 +
2 files changed, 146 insertions(+), 127 deletions(-)
d
This will be used by ARB_get_program_binary.
Tested-by: Dieter Nützel
---
src/mesa/state_tracker/st_shader_cache.c | 6 ++
src/mesa/state_tracker/st_shader_cache.h | 3 +++
2 files changed, 9 insertions(+)
diff --git a/src/mesa/state_tracker/st_shader_cache.c
b/src/mesa/state_tracker/st_sh
I've been contacted by people waiting for this to land so they can
play Dead Island so it would be really great if someone could review
this before the 18.0 freeze in two days.
The feature is enable for any driver that currently enables a tgsi
disk cache so it will be enabled for r600, radeonsi an
We will need this for ARB_get_program_binary binary support.
Tested-by: Dieter Nützel
---
src/mesa/state_tracker/st_program.c | 21 -
src/mesa/state_tracker/st_program.h | 12
src/mesa/state_tracker/st_shader_cache.c | 15 +--
src/mesa/state
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