---
src/amd/vulkan/radv_pipeline.c | 115 ++++++++++++++++++-----------------------
src/amd/vulkan/radv_private.h | 10 ----
2 files changed, 50 insertions(+), 75 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index e1d6fe159d..232c06c9a8 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -738,47 +738,6 @@ static uint32_t si_translate_fill(VkPolygonMode func)
return V_028814_X_DRAW_POINTS;
}
}
-static void
-radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
- const VkGraphicsPipelineCreateInfo *pCreateInfo)
-{
- const VkPipelineRasterizationStateCreateInfo *vkraster =
pCreateInfo->pRasterizationState;
- struct radv_raster_state *raster = &pipeline->graphics.raster;
-
- raster->spi_interp_control =
- S_0286D4_FLAT_SHADE_ENA(1) |
- S_0286D4_PNT_SPRITE_ENA(1) |
- S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
- S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
- S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
- S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
- S_0286D4_PNT_SPRITE_TOP_1(0); // vulkan is top to bottom - 1.0
at bottom
-
-
- raster->pa_cl_clip_cntl = S_028810_PS_UCP_MODE(3) |
- S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
- S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable ? 1 : 0)
|
- S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable ? 1 : 0) |
-
S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
- S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
-
- raster->pa_su_vtx_cntl =
- S_028BE4_PIX_CENTER(1) | // TODO verify
- S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
- S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH);
-
- raster->pa_su_sc_mode_cntl =
- S_028814_FACE(vkraster->frontFace) |
- S_028814_CULL_FRONT(!!(vkraster->cullMode &
VK_CULL_MODE_FRONT_BIT)) |
- S_028814_CULL_BACK(!!(vkraster->cullMode &
VK_CULL_MODE_BACK_BIT)) |
- S_028814_POLY_MODE(vkraster->polygonMode !=
VK_POLYGON_MODE_FILL) |
-
S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
-
S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
- S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1
: 0) |
- S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1
: 0) |
- S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1
: 0);
-
-}
static void
radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
@@ -2339,18 +2298,42 @@ radv_pipeline_generate_blend_state(struct
radv_pm4_builder *builder,
static void
radv_pipeline_generate_raster_state(struct radv_pm4_builder *builder,
- struct radv_pipeline *pipeline)
+ const VkGraphicsPipelineCreateInfo
*pCreateInfo)
{
- struct radv_raster_state *raster = &pipeline->graphics.raster;
+ const VkPipelineRasterizationStateCreateInfo *vkraster =
pCreateInfo->pRasterizationState;
radv_pm4_set_reg(builder, R_028810_PA_CL_CLIP_CNTL,
- raster->pa_cl_clip_cntl);
+ S_028810_PS_UCP_MODE(3) |
+ S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX
conventions.
+ S_028810_ZCLIP_NEAR_DISABLE(vkraster->depthClampEnable
? 1 : 0) |
+ S_028810_ZCLIP_FAR_DISABLE(vkraster->depthClampEnable
? 1 : 0) |
+
S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
+ S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
+
radv_pm4_set_reg(builder, R_0286D4_SPI_INTERP_CONTROL_0,
- raster->spi_interp_control);
+ S_0286D4_FLAT_SHADE_ENA(1) |
+ S_0286D4_PNT_SPRITE_ENA(1) |
+
S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
+
S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
+
S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
+
S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
+ S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to
bottom - 1.0 at bottom */
+
radv_pm4_set_reg(builder, R_028BE4_PA_SU_VTX_CNTL,
- raster->pa_su_vtx_cntl);
+ S_028BE4_PIX_CENTER(1) | // TODO verify
+ S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
+
S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
+
radv_pm4_set_reg(builder, R_028814_PA_SU_SC_MODE_CNTL,
- raster->pa_su_sc_mode_cntl);
+ S_028814_FACE(vkraster->frontFace) |
+ S_028814_CULL_FRONT(!!(vkraster->cullMode &
VK_CULL_MODE_FRONT_BIT)) |
+ S_028814_CULL_BACK(!!(vkraster->cullMode &
VK_CULL_MODE_BACK_BIT)) |
+ S_028814_POLY_MODE(vkraster->polygonMode !=
VK_POLYGON_MODE_FILL) |
+
S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
+
S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
+
S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
+
S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
+
S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
}
@@ -2936,14 +2919,15 @@ radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline,
const struct radv_graphics_pipeline_create_info
*extra,
const struct radv_blend_state *blend,
const struct radv_tessellation_state *tess,
- const struct radv_gs_state *gs) {
+ const struct radv_gs_state *gs,
+ uint32_t prim, uint32_t gs_out) {
struct radv_pm4_builder builder;
radv_pm4_init(&builder, &pipeline->pm4);
radv_pipeline_generate_depth_stencil_state(&builder, pipeline,
pCreateInfo, extra);
radv_pipeline_generate_blend_state(&builder, pipeline->device, blend);
- radv_pipeline_generate_raster_state(&builder, pipeline);
+ radv_pipeline_generate_raster_state(&builder, pCreateInfo);
radv_pipeline_generate_multisample_state(&builder, pipeline);
radv_pipeline_generate_vgt_gs_mode(&builder, pipeline);
radv_pipeline_generate_vertex_shader(&builder, pipeline, tess);
@@ -2961,11 +2945,11 @@ radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline,
radv_pm4_set_reg(&builder, R_028B54_VGT_SHADER_STAGES_EN,
radv_compute_vgt_shader_stages_en(pipeline));
if (pipeline->device->physical_device->rad_info.chip_class >= CIK) {
- radv_pm4_set_reg_idx(&builder, R_030908_VGT_PRIMITIVE_TYPE, 1,
pipeline->graphics.prim);
+ radv_pm4_set_reg_idx(&builder, R_030908_VGT_PRIMITIVE_TYPE, 1,
prim);
} else {
- radv_pm4_set_reg(&builder, R_008958_VGT_PRIMITIVE_TYPE,
pipeline->graphics.prim);
+ radv_pm4_set_reg(&builder, R_008958_VGT_PRIMITIVE_TYPE, prim);
}
- radv_pm4_set_reg(&builder, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
pipeline->graphics.gs_out);
+ radv_pm4_set_reg(&builder, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
radv_pm4_set_reg(&builder, R_02820C_PA_SC_CLIPRECT_RULE,
radv_compute_cliprect_rule(pCreateInfo));
@@ -2974,7 +2958,8 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
static struct radv_ia_multi_vgt_param_helpers
radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
- const struct radv_tessellation_state
*tess)
+ const struct radv_tessellation_state
*tess,
+ uint32_t prim)
{
struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
const struct radv_device *device = pipeline->device;
@@ -2999,7 +2984,6 @@ radv_compute_ia_multi_vgt_param_helpers(struct
radv_pipeline *pipeline,
ia_multi_vgt_param.wd_switch_on_eop = false;
if (device->physical_device->rad_info.chip_class >= CIK) {
- unsigned prim = pipeline->graphics.prim;
/* WD_SWITCH_ON_EOP has no effect on GPUs with less than
* 4 shader engines. Set 1 to pass the assertion below.
* The other cases are hardware requirements. */
@@ -3138,25 +3122,26 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
radv_generate_graphics_pipeline_key(pipeline,
pCreateInfo, &blend, has_view_index),
pStages);
- radv_pipeline_init_raster_state(pipeline, pCreateInfo);
radv_pipeline_init_multisample_state(pipeline, pCreateInfo);
- pipeline->graphics.prim =
si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
+ uint32_t gs_out;
+ uint32_t prim =
si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
+
pipeline->graphics.can_use_guardband =
radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
if (radv_pipeline_has_gs(pipeline)) {
- pipeline->graphics.gs_out =
si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
- pipeline->graphics.can_use_guardband =
pipeline->graphics.gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
+ gs_out =
si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
+ pipeline->graphics.can_use_guardband = gs_out ==
V_028A6C_OUTPRIM_TYPE_TRISTRIP;
} else {
- pipeline->graphics.gs_out =
si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
+ gs_out =
si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
}
if (extra && extra->use_rectlist) {
- pipeline->graphics.prim = V_008958_DI_PT_RECTLIST;
- pipeline->graphics.gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
+ prim = V_008958_DI_PT_RECTLIST;
+ gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
pipeline->graphics.can_use_guardband = true;
}
pipeline->graphics.prim_restart_enable =
!!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
/* prim vertex count will need TESS changes */
- pipeline->graphics.prim_vertex_count =
prim_size_table[pipeline->graphics.prim];
+ pipeline->graphics.prim_vertex_count = prim_size_table[prim];
pipeline->graphics.needed_dynamic_state =
radv_pipeline_needed_dynamic_state(pCreateInfo);
radv_pipeline_init_dynamic_state(pipeline, pCreateInfo,
pipeline->graphics.needed_dynamic_state);
@@ -3194,14 +3179,14 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
struct radv_tessellation_state tess = {0};
if (radv_pipeline_has_tess(pipeline)) {
- if (pipeline->graphics.prim == V_008958_DI_PT_PATCH) {
+ if (prim == V_008958_DI_PT_PATCH) {
pipeline->graphics.prim_vertex_count.min =
pCreateInfo->pTessellationState->patchControlPoints;
pipeline->graphics.prim_vertex_count.incr = 1;
}
tess = calculate_tess_state(pipeline, pCreateInfo);
}
- pipeline->graphics.ia_multi_vgt_param =
radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess);
+ pipeline->graphics.ia_multi_vgt_param =
radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
radv_compute_vertex_input_state(pipeline, pCreateInfo);
@@ -3224,7 +3209,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
}
result = radv_pipeline_scratch_init(device, pipeline);
- radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess,
&gs);
+ radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess,
&gs, prim, gs_out);
return result;
}
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 6cf8f2b75a..632799aecb 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1122,13 +1122,6 @@ mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
unsigned radv_format_meta_fs_key(VkFormat format);
-struct radv_raster_state {
- uint32_t pa_cl_clip_cntl;
- uint32_t spi_interp_control;
- uint32_t pa_su_vtx_cntl;
- uint32_t pa_su_sc_mode_cntl;
-};
-
struct radv_multisample_state {
uint32_t db_eqaa;
uint32_t pa_sc_line_cntl;
@@ -1203,10 +1196,7 @@ struct radv_pipeline {
uint32_t user_data_0[MESA_SHADER_STAGES];
union {
struct {
- struct radv_raster_state raster;
struct radv_multisample_state ms;
- unsigned prim;
- unsigned gs_out;
bool prim_restart_enable;
unsigned esgs_ring_size;
unsigned gsvs_ring_size;
--
2.15.1
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