---
src/amd/vulkan/radv_pipeline.c | 10 +++-------
src/amd/vulkan/radv_private.h | 1 -
2 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index dbe33d3cc5..b39ee4308b 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2802,7 +2802,9 @@ radv_pipeline_generate_fragment_shader(struct
radv_pm4_builder *builder,
radv_pm4_set_reg(builder, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
radv_pm4_set_reg(builder, R_028710_SPI_SHADER_Z_FORMAT,
- pipeline->graphics.shader_z_format);
+ ac_get_spi_shader_z_format(ps->info.fs.writes_z,
+ ps->info.fs.writes_stencil,
+
ps->info.fs.writes_sample_mask));
radv_pm4_set_reg(builder, R_028714_SPI_SHADER_COL_FORMAT,
blend->spi_shader_col_format);
@@ -2966,12 +2968,6 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
if (pipeline->device->physical_device->has_rbplus)
pipeline->graphics.db_shader_control |=
S_02880C_DUAL_QUAD_DISABLE(1);
- unsigned shader_z_format =
- ac_get_spi_shader_z_format(ps->info.fs.writes_z,
- ps->info.fs.writes_stencil,
- ps->info.fs.writes_sample_mask);
- pipeline->graphics.shader_z_format = shader_z_format;
-
calculate_vgt_gs_mode(pipeline);
for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index b11ad6d66a..f8c206dbee 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1230,7 +1230,6 @@ struct radv_pipeline {
struct radv_tessellation_state tess;
struct radv_gs_state gs;
uint32_t db_shader_control;
- uint32_t shader_z_format;
unsigned prim;
unsigned gs_out;
uint32_t vgt_gs_mode;
--
2.15.1
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