Reviewed-by: Alejandro Piñeiro
On 14/04/17 23:55, Jason Ekstrand wrote:
> ---
> src/compiler/nir/nir.c | 2 ++
> src/compiler/nir/nir_split_var_copies.c | 2 ++
> 2 files changed, 4 insertions(+)
>
> diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
> index 43fa60f..0
On Sat, Apr 15, 2017 at 07:49:53AM +0200, Wladimir J. van der Laan wrote:
> On Fri, Apr 14, 2017 at 11:57:21PM +0200, Christian Gmeiner wrote:
> > > +#define INST_OPCODE_IMADLOSAT0 0x004e
> > > +#define INST_OPCODE_IMADLOSAT0 0x000
On Fri, Apr 14, 2017 at 11:57:21PM +0200, Christian Gmeiner wrote:
> > +#define INST_OPCODE_IMADLOSAT0 0x004e
> > +#define INST_OPCODE_IMADLOSAT0 0x004f
>
> INST_OPCODE_IMADLOSAT0 got redefined...
Second one should be IMADLOS
On Fri, Apr 14, 2017 at 8:35 PM, Anuj Phogat wrote:
> From: Ben Widawsky
>
> GEN10 requires flushing all previous pipe controls before issuing a render
> target cache flush. The docs seem to fairly explicitly say this is gen10 only.
>
> v2: Rebased on
> commit 04f74d66293222d5e1905cfb930bfa083e30
Reviewed-by: Timothy Arceri
On 15/04/17 04:42, Brian Paul wrote:
---
src/mesa/main/texobj.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c
index ad644ca..00feb97 100644
--- a/src/mesa/main/texobj.c
+++ b/src/mesa/main/texob
From: Ben Widawsky
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_defines.h | 1 +
src/mesa/drivers/dri/i965/gen8_vs_state.c | 6 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_define
From: Ben Widawsky
V2: Squash the changes in one patch and rebased on master (Anuj).
Signed-off-by: Ben Widawsky
Signed-off-by: Anuj Phogat
---
src/intel/common/gen_l3_config.c | 43 ++--
1 file changed, 37 insertions(+), 6 deletions(-)
diff --git a/src/in
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_program.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_program.c
b/src/mesa/drivers/dri/i965/brw_program.c
index e1f9896..ab719ad 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_blorp.c| 7 ++-
src/mesa/drivers/dri/i965/brw_defines.h | 8
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 ++
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/
v1: By Ben Widawsky
v2: Add the restriction for GS, HS and DS and make sure
the allocated sizes are not multiple of 3.
Signed-off-by: Anuj Phogat
Cc: Ben Widawsky
---
src/mesa/drivers/dri/i965/gen7_urb.c | 12
1 file changed, 12 insertions(+)
diff --git a/src/mesa/drivers/dri
From: Ben Widawsky
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_queryobj.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c
b/src/mesa/drivers/dri/i965/brw_queryobj.c
index 5c3ecba..d0d0589 100644
--- a/src/mesa/drivers/dri/i
From: Ben Widawsky
This support was removed on gen9 (it worked before then) and was brought back
for gen10.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_t
From: Ben Widawsky
Since we've implemented all the known quirks for supporting gen10 with none of
the new features (ie. functions like Skylake), it should be safe to actually
enable the device.
v2: rebased on top of master and updated pci ids (Anuj)
Signed-off-by: Ben Widawsky
Signed-off-by: A
Signed-off-by: Anuj Phogat
---
src/intel/genxml/gen_bits_header.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/genxml/gen_bits_header.py
b/src/intel/genxml/gen_bits_header.py
index 808e6cf..77cd966 100644
--- a/src/intel/genxml/gen_bits_header.py
+++ b/src/i
This series adds a preliminary support for Cannonlake. We
still end up using gen9 paths in many cases. My upcoming
patches will change it by creating new functions, headers
for gen10. You can also find this series at:
https://github.com/aphogat/mesa.git
branch: reviews
Anuj Phogat (4):
i965/cnl
From: Ben Widawsky
GEN10 requires flushing all previous pipe controls before issuing a render
target cache flush. The docs seem to fairly explicitly say this is gen10 only.
v2: Rebased on
commit 04f74d66293222d5e1905cfb930bfa083e30463c
Author: Francisco Jerez
Date: Thu Jun 30 19:39:24 2016 -0
From: Ben Widawsky
All the "features" of the hardware are similar starting with GEN8, so remove as
much of the GEN9 uniqueness as possible. This makes implementing future gen
platforms a bit easier.
Signed-off-by: Ben Widawsky
Reviewed-by: Anuj Phogat
---
src/intel/common/gen_device_info.c |
Thanks Emil,
I will attempt to un-meh a bit at checkin.
George
> On Apr 14, 2017, at 5:52 PM, Emil Velikov wrote:
>
> Commit summary is a bit meh, but regardless.
>
> Reviewed-by: Emil Velikov
>
> -Emil
___
mesa-dev mailing list
mesa-dev@lists.fr
On 14 April 2017 at 22:43, Bas Nieuwenhuizen wrote:
> For the next time I forget.
>
> CC: Emil Velikov
> Signed-off-by: Bas Nieuwenhuizen
> ---
> docs/submittingpatches.html | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/docs/submittingpatches.html b/docs/submittingpatches.html
>
2017-04-12 12:31 GMT+02:00 Philipp Zabel :
> This adds native fence fd support to etnaviv, similarly to commit
> 0b98e84e9ba0 ("freedreno: native fence fd"), enabled for kernel
> driver version 1.1 or later.
>
> Signed-off-by: Philipp Zabel
> Reviewed-By: Wladimir J. van der Laan
Reviewed-by: Ch
Tested-by: Dieter Nützel
On Turks XT (6670)
Dieter
Am 13.04.2017 22:56, schrieb Constantine Kharlamov:
Ported from radeonsi. Testing with Kane&Lynch2 shows ≈1k skipped
updates per
frame on average.
No piglit changes with tests/gpu.py, gbm mode.
Signed-off-by: Constantine Kharlamov
---
sr
Commit summary is a bit meh, but regardless.
Reviewed-by: Emil Velikov
-Emil
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mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Am 14.04.2017 07:53, schrieb gregory hainaut:
On Fri, 14 Apr 2017 05:20:38 +0200
Dieter Nützel wrote:
Am 14.04.2017 02:06, schrieb Dieter Nützel:
> Hello Gregory,
>
> have you tested this with Mesa-demos/tests/pbo 'b' (benchmark)?
> It result in crazy numbers and do not 'return' (one core stay
Cc: mesa-sta...@lists.freedesktop.org
---
src/compiler/nir/nir.c | 2 ++
src/compiler/nir/nir_split_var_copies.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index 43fa60f..0abf9b6 100644
--- a/src/compiler/nir/nir.c
+++ b/
2017-04-12 16:13 GMT+02:00 Lucas Stach :
> From: Philipp Zabel
>
> When passing render buffers from EGL clients to a wayland compositor,
> the resource tile status must be resolved because otherwise the tile
> status is lost in the transfer and cleared parts of the buffer will
> contain old conten
2017-04-12 16:13 GMT+02:00 Lucas Stach :
> From: Philipp Zabel
>
> Before resolving a resource into its scanout prime buffer, check that
> the prime resource is actually older. If it is not, the resolve is an
> expensive no-op, and we better skip it.
>
> Signed-off-by: Philipp Zabel
Reviewed-by:
> +#define INST_OPCODE_IMADLOSAT0 0x004e
> +#define INST_OPCODE_IMADLOSAT0 0x004f
INST_OPCODE_IMADLOSAT0 got redefined...
greets
--
Christian Gmeiner, MSc
https://www.youtube.com/user/AloryOFFICIAL
https://soundcloud.com/chr
---
src/compiler/nir/nir.c | 2 ++
src/compiler/nir/nir_split_var_copies.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index 43fa60f..0abf9b6 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -699,7 +699,
---
src/gallium/targets/osmesa/SConscript | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/targets/osmesa/SConscript
b/src/gallium/targets/osmesa/SConscript
index 47937a2..7be1b48 100644
--- a/src/gallium/targets/osmesa/SConscript
+++ b/src/gallium/targets/osmesa/SC
For the next time I forget.
CC: Emil Velikov
Signed-off-by: Bas Nieuwenhuizen
---
docs/submittingpatches.html | 5 +
1 file changed, 5 insertions(+)
diff --git a/docs/submittingpatches.html b/docs/submittingpatches.html
index 5310b1d8c17..4b025647039 100644
--- a/docs/submittingpatches.htm
On 14 April 2017 at 19:21, Eric Anholt wrote:
> Emil Velikov writes:
>
>> On 14 April 2017 at 18:47, Eric Anholt wrote:
>>> NEON is sufficiently different on arm64 that we can't just reuse this
>>> code. Disable it on arm64 for now.
>>>
>>> Signed-off-by: Eric Anholt
>>> ---
>>> src/gallium/d
2017-04-14 9:44 GMT+02:00 Wladimir J. van der Laan :
> This patch adds support for the SINGLE_BUFFER feature on GC3000
> GPUs, which allows rendering to a single buffer using multiple pixel
> pipes.
>
> This feature is always used when it is available, which means that
> multi-tiled formats are no
Reviewed-by: Bas Nieuwenhuizen
On Fri, Apr 14, 2017 at 11:24 PM, Grazvydas Ignotas wrote:
> Commit bfee9866 "radv: Use RELEASE_MEM packet for MEC timestamp query."
> added WriteTimestamp handling for compute queues but forgot to flip
> the flag.
>
> Tested with DOOM (by me) and CTS (by Bas), but
Commit bfee9866 "radv: Use RELEASE_MEM packet for MEC timestamp query."
added WriteTimestamp handling for compute queues but forgot to flip
the flag.
Tested with DOOM (by me) and CTS (by Bas), but without verification
that these tests actually use timestamps on compute queues.
Signed-off-by: Graz
On 14.04.2017 17:08, Marek Olšák wrote:
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 6242ec1..704c67e 100644
-
On Wed, Apr 12, 2017 at 2:54 PM, Nanley Chery wrote:
> On Tue, Apr 11, 2017 at 07:54:23AM -0700, Jason Ekstrand wrote:
> > The Vulkan driver was originally written under the assumption that
> > VK_ATTACHMENT_UNUSED was basically just for depth-stencil attachments.
> > However, the way things fell
Reviewed-by: Bruce Cherniak
> On Apr 14, 2017, at 2:03 PM, Tim Rowley wrote:
>
> v2: add back scons section, mention additional built swr libraries
> ---
> src/gallium/docs/source/drivers/openswr.rst | 2 +-
> src/gallium/docs/source/drivers/openswr/usage.rst | 16 +++-
> 2 fil
Reviewed-by: George Kyriazis
mailto:george.kyria...@intel.com>>
With the assumption that there are additional changes forthcoming.
On Apr 13, 2017, at 5:40 PM, Bruce Cherniak
mailto:bruce.chern...@intel.com>> wrote:
This patch enables multisample antialiasing in the OpenSWR software renderer.
For the series:
Reviewed-by: Marek Olšák
Marek
On Fri, Apr 14, 2017 at 6:32 PM, Samuel Pitoiset
wrote:
> Signed-off-by: Samuel Pitoiset
> ---
> src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 10 ++
> 1 file changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/src/gallium/winsys/amd
For the series:
Reviewed-by: Marek Olšák
Marek
On Thu, Apr 13, 2017 at 10:30 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> ---
> docs/features.txt | 2 +-
> docs/relnotes/17.1.0.html | 1 +
> src/gallium/drivers/radeonsi/si_pipe.c | 2 +-
> 3 files ch
Reviewed-by: Jason Ekstrand
On Fri, Apr 14, 2017 at 12:18 PM, Nanley Chery
wrote:
> The description under RENDER_SURFACE_STATE::RedClearColor says,
>
>For Sampling Engine Multisampled Surfaces and Render Targets:
> Specifies the clear value for the red channel.
>For Other Surfaces:
For the series:
Reviewed-by: Marek Olšák
Marek
On Thu, Apr 13, 2017 at 8:23 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> For robustness and testing purposes.
> ---
> src/gallium/drivers/radeonsi/si_state_shaders.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --g
The description under RENDER_SURFACE_STATE::RedClearColor says,
For Sampling Engine Multisampled Surfaces and Render Targets:
Specifies the clear value for the red channel.
For Other Surfaces:
This field is ignored.
This means that the sampler on BDW doesn't support CCS.
Cc: Samuel
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Fri, Apr 14, 2017 at 12:26 AM, Fredrik Höglund wrote:
> This allows meta to use push descriptors without disturbing user
> push descriptors.
>
> radv_meta_push_descriptor_set differs from vkCmdPushDescriptorSetKHR
> in that partial updates are n
v2: add back scons section, mention additional built swr libraries
---
src/gallium/docs/source/drivers/openswr.rst | 2 +-
src/gallium/docs/source/drivers/openswr/usage.rst | 16 +++-
2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/src/gallium/docs/source/drivers
On Fri, Apr 14, 2017 at 2:52 PM, Kyriazis, George
wrote:
> > > + /* work around the fact that poly stipple also affects lines */
> > > + /* and points, since we rasterize them as triangles, too */
> > > + /* Has to be before fragment shader, since it sets SWR_NEW_FS */
> > > + if (p_draw_i
On Apr 14, 2017, at 11:35 AM, Ilia Mirkin
mailto:imir...@alum.mit.edu>> wrote:
On Fri, Apr 14, 2017 at 11:18 AM, Ilia Mirkin
mailto:imir...@alum.mit.edu>> wrote:
On Thu, Apr 13, 2017 at 4:30 PM, George Kyriazis
mailto:george.kyria...@intel.com>> wrote:
Add polygon stipple functionality to the f
---
src/mesa/main/texobj.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c
index ad644ca..00feb97 100644
--- a/src/mesa/main/texobj.c
+++ b/src/mesa/main/texobj.c
@@ -1663,7 +1663,8 @@ _mesa_BindTexture( GLenum target, GLuint te
Hello list,
The candidate for the Mesa 17.0.4 is now available. Currently we have:
- 28 queued
- 1 nominated (outstanding)
- and 0 rejected patch(es)
Current queue includes of extra PCI IDs and a runtime warning fix for radeonsi.
While r600 has improved error handling in OOM conditions.
Ther
Timothy Arceri writes:
> Improves Deus Ex start-up times with a warm cache from ~30 seconds to
> ~22 seconds.
>
> Also fixes the leaking of state.
The commit message could use some more context:
"This moves the hashing of shader source for the cache lookup to before
the preprocessor. In our ex
Emil Velikov writes:
> On 14 April 2017 at 10:38, Yu, Qiang wrote:
>>
>> Hi Emil,
>>
>>> What happened with the idea of reusing your existing amdgpu_dri.so ?
>>> As mentioned before the DRI loader (libgbm) <> DRI driver (foo_dri.so)
>>> interface is stable, so things should just work.
>> Sorry f
On Apr 14, 2017, at 12:44 PM, Emil Velikov
mailto:emil.l.veli...@gmail.com>> wrote:
On 13 April 2017 at 20:17, George Kyriazis
mailto:george.kyria...@intel.com>> wrote:
Make swr compile for both linux and windows.
---
src/gallium/drivers/swr/SConscript| 7 +--
src/gallium/targets/lib
Emil Velikov writes:
> On 14 April 2017 at 18:47, Eric Anholt wrote:
>> NEON is sufficiently different on arm64 that we can't just reuse this
>> code. Disable it on arm64 for now.
>>
>> Signed-off-by: Eric Anholt
>> ---
>> src/gallium/drivers/vc4/vc4_tiling_lt.c | 4 ++--
>> 1 file changed, 2
On 14 April 2017 at 18:47, Eric Anholt wrote:
> NEON is sufficiently different on arm64 that we can't just reuse this
> code. Disable it on arm64 for now.
>
> Signed-off-by: Eric Anholt
> ---
> src/gallium/drivers/vc4/vc4_tiling_lt.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Reviewed-by: Bas Nieuwenhuizen
On Fri, Apr 14, 2017 at 7:17 PM, Grazvydas Ignotas wrote:
> A leftover from anv.
>
> Signed-off-by: Grazvydas Ignotas
> ---
> src/amd/vulkan/radv_device.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_device.c b/src/
For some reason I thought it did it in 10 KHz.
Reviewed-by: Bas Nieuwenhuizen
On Fri, Apr 14, 2017 at 7:17 PM, Grazvydas Ignotas wrote:
> The kernel returns frequency in kHz, so to convert to nanosecond
> interval that Vulkan uses the dividend should be 100.0 and not
> 10.0.
>
> This fi
On 14 April 2017 at 10:38, Yu, Qiang wrote:
>
> Hi Emil,
>
>> What happened with the idea of reusing your existing amdgpu_dri.so ?
>> As mentioned before the DRI loader (libgbm) <> DRI driver (foo_dri.so)
>> interface is stable, so things should just work.
> Sorry for the late reply. I've asked ou
On 13 April 2017 at 19:41, Tim Rowley wrote:
> ---
> src/gallium/docs/source/drivers/openswr.rst | 2 +-
> src/gallium/docs/source/drivers/openswr/usage.rst | 9 +++--
> 2 files changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/src/gallium/docs/source/drivers/openswr.rst
> b/sr
I wrote this code with reference to pixman, though I've only decided to
cover Linux (what I'm testing) and Android (seems obvious enough). Linux
has getauxval() as a cleaner interface to the /proc entry, but it's more
glibc-specific and I didn't want to add detection for that.
This will be used t
NEON is sufficiently different on arm64 that we can't just reuse this
code. Disable it on arm64 for now.
Signed-off-by: Eric Anholt
---
src/gallium/drivers/vc4/vc4_tiling_lt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/vc4/vc4_tiling_lt.c
b/src/
This will allow Raspbian's ARMv6 builds to take advantage of the new NEON
code, and could prevent problems if vc4 ends up getting used on a v7 CPU
without NEON.
---
src/gallium/drivers/vc4/vc4_screen.c | 3 +++
src/gallium/drivers/vc4/vc4_tiling.h | 25 +
2 files changed,
Android.mk was setting the flag across the entire driver, so we didn't
have non-NEON versions getting built. This was going to be a problem with
the next commit, when I start auto-detecting NEON support and use the
non-NEON version when appropriate.
---
src/gallium/drivers/vc4/Android.mk
On 13 April 2017 at 20:17, George Kyriazis wrote:
> Make swr compile for both linux and windows.
> ---
> src/gallium/drivers/swr/SConscript| 7 +--
> src/gallium/targets/libgl-xlib/SConscript | 2 +-
> 2 files changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/src/gallium/drive
---
src/intel/vulkan/anv_batch_chain.c | 69
src/intel/vulkan/anv_device.c | 2 +
src/intel/vulkan/anv_private.h | 8
src/intel/vulkan/anv_queue.c | 93 --
4 files changed, 148 insertions(+), 24 deletions(-)
di
---
src/intel/vulkan/anv_gem.c | 79
src/intel/vulkan/anv_gem_stubs.c | 24
src/intel/vulkan/anv_private.h | 4 ++
3 files changed, 107 insertions(+)
diff --git a/src/intel/vulkan/anv_gem.c b/src/intel/vulkan/anv_gem.c
index e331fbb..
---
src/intel/vulkan/anv_gem.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_gem.c b/src/intel/vulkan/anv_gem.c
index 185086f..1392bf4 100644
--- a/src/intel/vulkan/anv_gem.c
+++ b/src/intel/vulkan/anv_gem.c
@@ -185,7 +185,10 @@ int
anv_gem_execbuffe
This implementation allocates a 4k BO for each semaphore that can be
exported using OPAQUE_FD and uses the kernel's already-existing
synchronization mechanism on BOs.
---
src/intel/vulkan/anv_batch_chain.c | 53 ++--
src/intel/vulkan/anv_device.c | 4 +
src/intel/vulkan/a
---
src/intel/vulkan/anv_batch_chain.c | 96 --
src/intel/vulkan/anv_device.c | 25 ++
src/intel/vulkan/anv_gem.c | 36 ++
src/intel/vulkan/anv_private.h | 24 +++---
src/intel/vulkan/anv_queue.c | 73 ++
This patch will never be committed because Vulkan queue priorities are
supposed to be local to the device and not cross process boundaries.
---
src/intel/vulkan/anv_device.c| 12
src/intel/vulkan/anv_gem.c | 13 +
src/intel/vulkan/anv_gem_stubs.c | 7 +++
s
---
src/intel/vulkan/anv_device.c | 4
src/intel/vulkan/anv_entrypoints_gen.py | 1 +
src/intel/vulkan/anv_queue.c| 8
3 files changed, 13 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 41e0fb3..b85cd40 100644
---
---
src/intel/vulkan/anv_batch_chain.c | 59 ++
1 file changed, 35 insertions(+), 24 deletions(-)
diff --git a/src/intel/vulkan/anv_batch_chain.c
b/src/intel/vulkan/anv_batch_chain.c
index 3e9fa4c..136f273 100644
--- a/src/intel/vulkan/anv_batch_chain.c
+++ b/
It's just a dummy for now, but we'll flesh it out as needed for external
semaphores.
---
src/intel/vulkan/anv_private.h | 28
src/intel/vulkan/anv_queue.c | 32 ++--
2 files changed, 54 insertions(+), 6 deletions(-)
diff --git a/src/intel
Reviewed-by: Chad Versace
---
src/intel/vulkan/anv_device.c | 27 ---
src/intel/vulkan/anv_image.c | 2 +-
src/intel/vulkan/anv_intel.c | 15 ++-
src/intel/vulkan/anv_private.h | 4 +++-
src/intel/vulkan/anv_wsi.c | 8
5 files changed, 30 i
This just stubs things out. Real external semaphore support will come
with VK_KHX_external_semaphore_fd.
---
src/intel/vulkan/anv_device.c | 4
src/intel/vulkan/anv_entrypoints_gen.py | 1 +
src/intel/vulkan/anv_queue.c| 13 +
3 files changed, 18 insertion
This commit just exposes the memory handle type. There's interesting we
need to do here for images. So long as the user doesn't set any crazy
environment variables such as INTEL_DEBUG=nohiz, all of the compression
formats etc. should "just work" at least for opaque handle types.
v2 (chadv):
-
This cache allows us to easily ensure that we have a unique anv_bo for
each gem handle. We'll need this in order to support multiple-import of
memory objects and semaphores.
v2 (Jason Ekstrand):
- Reject BO imports if the size doesn't match the prime fd size as
reported by lseek().
---
src/i
Things are about to get more complicated, especially as far as
semaphores are concerned.
Reviewed-by: Chad Versace
---
src/intel/Makefile.sources| 1 +
src/intel/vulkan/anv_device.c | 484 ---
src/intel/vulkan/anv_queue.c | 515 +
This is the trivial implementation that just exposes the extension
string but exposes zero external handle types.
Reviewed-by: Chad Versace
---
src/intel/vulkan/anv_device.c | 4
src/intel/vulkan/anv_entrypoints_gen.py | 1 +
2 files changed, 5 insertions(+)
diff --git a/src/inte
From: Chad Versace
This is a complete but trivial implementation. It's trivial becasue We
support no external memory capabilities yet. Most of the real work in
this commit is in reworking the UUIDs advertised by the driver.
v2 (chadv):
- Fix chain traversal in vkGetPhysicalDeviceImageFormatPr
Reviewed-by: Chad Versace
---
src/intel/vulkan/anv_device.c | 30 +-
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 079b0c5..ad10531 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/sr
This prevents a user from using a cache created on one hardware
generation on a different one. Of course, with Intel hardware, this
requires moving their drive from one machine to another but it's still
possible and we should prevent it.
Reviewed-by: Chad Versace
---
src/intel/vulkan/anv_device
We're about to have more UUIDs for different things so this one really
needs to be properly labeled.
Reviewed-by: Chad Versace
---
src/intel/vulkan/anv_device.c | 5 +++--
src/intel/vulkan/anv_pipeline_cache.c | 4 ++--
src/intel/vulkan/anv_private.h| 2 +-
3 files changed, 6 ins
This patch series adds support for a bunch of the VK_KHX_external
extensions. This is mostly a re-send but there are a few bugfixes tucked
in here and there are also some new patches. Changes of note:
1) It's been freshly rebased on master
2) The BO cache has undergone quite a few bugfixes.
---
src/intel/vulkan/anv_allocator.c | 3 +++
src/intel/vulkan/anv_device.c| 5 +
src/intel/vulkan/anv_private.h | 1 +
src/intel/vulkan/anv_wsi.c | 1 +
4 files changed, 10 insertions(+)
diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index 784191
The command is really operating on a Queue not a command buffer and the
nearest object to that with an allocator is VkDevice.
Cc: "17.0"
---
src/intel/vulkan/anv_batch_chain.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/intel/vulkan/anv_batch_chain.c
b/src/inte
On 13 April 2017 at 19:22, Ben Widawsky wrote:
> ---
> common.c | 13 -
> common.h | 11 ++-
> kmscube.c | 14 +++---
> 3 files changed, 29 insertions(+), 9 deletions(-)
>
> diff --git a/common.c b/common.c
> index e63bb39..eaaa9a4 100644
> --- a/common.c
> +++ b/com
On 13 April 2017 at 19:22, Ben Widawsky wrote:
> Note: nothing happens here yet since LINEAR == 0.
Suggestion for the subject
common: use drmModeAddFB2* API over the legacy drmModeAddFB one
> ---
> configure.ac | 2 +-
> drm-common.c | 37 +
> 2 files chan
A leftover from anv.
Signed-off-by: Grazvydas Ignotas
---
src/amd/vulkan/radv_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 5f14394..7857e8f 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vu
The kernel returns frequency in kHz, so to convert to nanosecond
interval that Vulkan uses the dividend should be 100.0 and not
10.0.
This fixes the GPU graph in DOOM and matches the amdgpu-pro blob.
Signed-off-by: Grazvydas Ignotas
Fixes: f4e499ec791 "radv: add initial non-conformant ra
On 13 April 2017 at 19:22, Ben Widawsky wrote:
> ---
> common.c | 19 +++
> 1 file changed, 19 insertions(+)
>
> diff --git a/common.c b/common.c
> index 4bf3c5a..e63bb39 100644
> --- a/common.c
> +++ b/common.c
> @@ -31,10 +31,23 @@
>
> static struct gbm gbm;
>
> +#ifndef DRM_FO
Hi Ben,
On 13 April 2017 at 19:22, Ben Widawsky wrote:
> ---
> common.h | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/common.h b/common.h
> index 2eceac7..f3d9d32 100644
> --- a/common.h
> +++ b/common.h
> @@ -32,6 +32,10 @@
> #include
> #include
>
> +#ifdef HAVE_CONFIG_H
> +
On 13 April 2017 at 17:14, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> Enable code sanitizers by adding -fsanitize=$foo flags for the compiler
> and linker.
>
> In addition, this also disables checking for undefined symbols: running
> the address sanitizer requires additional symbols which s
+Matt, +Ken
On Wed, Apr 12, 2017 at 6:09 PM, Boyan Ding wrote:
> 2017-04-13 2:25 GMT+08:00 Jason Ekstrand :
> > On Wed, Apr 12, 2017 at 6:14 AM, Boyan Ding
> wrote:
> >>
> >> This fixes the following error when using ARB_shader_clock on i965:
> >> vec1 32 ssa_0 = intrinsic shader_clock
On Fri, Apr 14, 2017 at 12:45 PM, Marek Olšák wrote:
> On Fri, Apr 14, 2017 at 5:12 PM, Ilia Mirkin wrote:
>> On Fri, Apr 14, 2017 at 11:06 AM, Marek Olšák wrote:
>>> diff --git a/src/mesa/vbo/vbo.h b/src/mesa/vbo/vbo.h
>>> index d62ab4e..79f7538 100644
>>> --- a/src/mesa/vbo/vbo.h
>>> +++ b/src
On Fri, Apr 14, 2017 at 12:42 PM, Marek Olšák wrote:
> On Fri, Apr 14, 2017 at 5:45 PM, Ilia Mirkin wrote:
>> On Fri, Apr 14, 2017 at 11:07 AM, Marek Olšák wrote:
>>> diff --git a/src/gallium/drivers/nouveau/nv30/nv30_vbo.c
>>> b/src/gallium/drivers/nouveau/nv30/nv30_vbo.c
>>> index bc9b9a1..29
On Wed, Apr 12, 2017 at 6:14 AM, Boyan Ding wrote:
> This fixes the following error when using ARB_shader_clock on i965:
> vec1 32 ssa_0 = intrinsic shader_clock () () ()
> intrinsic store_var (ssa_0) (clock_retval) (3) /* wrmask=xy */
> error: src->ssa->num_components == num_comp
On Fri, Apr 14, 2017 at 5:12 PM, Ilia Mirkin wrote:
> On Fri, Apr 14, 2017 at 11:06 AM, Marek Olšák wrote:
>> diff --git a/src/mesa/vbo/vbo.h b/src/mesa/vbo/vbo.h
>> index d62ab4e..79f7538 100644
>> --- a/src/mesa/vbo/vbo.h
>> +++ b/src/mesa/vbo/vbo.h
>
> Should also be possible to remove vbo_siz
On Fri, Apr 14, 2017 at 5:45 PM, Ilia Mirkin wrote:
> On Fri, Apr 14, 2017 at 11:07 AM, Marek Olšák wrote:
>> diff --git a/src/gallium/drivers/nouveau/nv30/nv30_vbo.c
>> b/src/gallium/drivers/nouveau/nv30/nv30_vbo.c
>> index bc9b9a1..295c394 100644
>> --- a/src/gallium/drivers/nouveau/nv30/nv30_
Thanks.
I'm amending this:
diff --git a/src/mesa/state_tracker/st_atom_array.c
b/src/mesa/state_tracker/st_atom_array.c
index 6cfbd24..436ea45 100644
--- a/src/mesa/state_tracker/st_atom_array.c
+++ b/src/mesa/state_tracker/st_atom_array.c
@@ -47,8 +47,9 @@
#include "main/bufferobj.h"
#include
On Fri, Apr 14, 2017 at 11:18 AM, Ilia Mirkin wrote:
> On Thu, Apr 13, 2017 at 4:30 PM, George Kyriazis
> wrote:
>> Add polygon stipple functionality to the fragment shader.
>>
>> Explicitly turn off polygon stipple for lines and points, since we
>> do them using tris.
>> ---
>> src/gallium/driv
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