From: Ben Widawsky <benjamin.widaw...@intel.com>
Since we've implemented all the known quirks for supporting gen10 with none of
the new features (ie. functions like Skylake), it should be safe to actually
enable the device.
v2: rebased on top of master and updated pci ids (Anuj)
Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com>
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
include/pci_ids/i965_pci_ids.h | 12 ++++++
src/intel/common/gen_device_info.c | 59 +++++++++++++++++++++++++++++
src/intel/common/gen_device_info.h | 1 +
src/intel/common/gen_l3_config.c | 1 +
src/intel/compiler/brw_compiler.h | 2 +-
src/intel/compiler/brw_eu.c | 2 +
src/intel/compiler/brw_eu_compact.c | 1 +
src/intel/isl/isl.c | 2 +
src/intel/vulkan/anv_cmd_buffer.c | 1 +
src/intel/vulkan/anv_device.c | 1 +
src/intel/vulkan/anv_entrypoints_gen.py | 1 +
src/mesa/drivers/dri/i965/brw_blorp.c | 1 +
src/mesa/drivers/dri/i965/brw_draw_upload.c | 1 +
src/mesa/drivers/dri/i965/brw_formatquery.c | 1 +
src/mesa/drivers/dri/i965/intel_screen.c | 1 +
15 files changed, 86 insertions(+), 1 deletion(-)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 17504f5..b296359 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -165,3 +165,15 @@ CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650
(Kaby Lake GT3)")
CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4")
CHIPSET(0x3184, glk, "Intel(R) HD Graphics (Geminilake)")
CHIPSET(0x3185, glk_2x6, "Intel(R) HD Graphics (Geminilake 2x6)")
+CHIPSET(0x5A49, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
+CHIPSET(0x5A4A, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8 GT0.5)")
+CHIPSET(0x5A41, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
+CHIPSET(0x5A42, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
+CHIPSET(0x5A44, cnl_3x8, "Intel(R) HD Graphics (Cannonlake 3x8 GT1)")
+CHIPSET(0x5A59, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)")
+CHIPSET(0x5A5A, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)")
+CHIPSET(0x5A5C, cnl_4x8, "Intel(R) HD Graphics (Cannonlake 4x8 GT1.5)")
+CHIPSET(0x5A50, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x5A51, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x5A52, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
+CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
diff --git a/src/intel/common/gen_device_info.c
b/src/intel/common/gen_device_info.c
index 47aed9d..43d6f08 100644
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -555,6 +555,65 @@ static const struct gen_device_info
gen_device_info_glk_2x6 = {
GEN9_LP_FEATURES_2X6
};
+#define GEN10_HW_INFO \
+ .gen = 10, \
+ .max_vs_threads = 728, \
+ .max_gs_threads = 432, \
+ .max_tcs_threads = 432, \
+ .max_tes_threads = 624, \
+ .max_wm_threads = 64 * 12, \
+ .max_cs_threads = 56, \
+ .urb = { \
+ .size = 256, \
+ .min_entries = { \
+ [MESA_SHADER_VERTEX] = 64, \
+ [MESA_SHADER_TESS_EVAL] = 34, \
+ }, \
+ .max_entries = { \
+ [MESA_SHADER_VERTEX] = 3936, \
+ [MESA_SHADER_TESS_CTRL] = 896, \
+ [MESA_SHADER_TESS_EVAL] = 2064, \
+ [MESA_SHADER_GEOMETRY] = 832, \
+ }, \
+ }
+
+#define GEN10_FEATURES(_gt, _slices, _l3) \
+ GEN8_FEATURES, \
+ GEN10_HW_INFO, \
+ .gt = _gt, .num_slices = _slices, .l3_banks = _l3
+
+static const struct gen_device_info gen_device_info_cnl_2x8 = {
+ /* GT0.5 */
+ GEN10_FEATURES(1, 1, 2)
+};
+
+static const struct gen_device_info gen_device_info_cnl_3x8 = {
+ /* GT1 */
+ GEN10_FEATURES(1, 1, 3)
+};
+
+static const struct gen_device_info gen_device_info_cnl_4x8 = {
+ /* GT 1.5 */
+ GEN10_FEATURES(1, 2, 6)
+};
+
+static const struct gen_device_info gen_device_info_cnl_5x8 = {
+ /* GT2 */
+ GEN10_FEATURES(2, 2, 6)
+};
+
+static const struct gen_device_info gen_device_info_cnl_gt1 = {
+ GEN10_FEATURES(1, 1, 3)
+};
+
+static const struct gen_device_info gen_device_info_cnl_gt2 = {
+ GEN10_FEATURES(2, 2, 6)
+};
+
+static const struct gen_device_info gen_device_info_cnl_gt3 = {
+ GEN10_FEATURES(3, 4, 12)
+};
+
bool
gen_get_device_info(int devid, struct gen_device_info *devinfo)
{
diff --git a/src/intel/common/gen_device_info.h
b/src/intel/common/gen_device_info.h
index 80676d0..6207630 100644
--- a/src/intel/common/gen_device_info.h
+++ b/src/intel/common/gen_device_info.h
@@ -96,6 +96,7 @@ struct gen_device_info
* to change, so we program @max_cs_threads as the lower maximum.
*/
unsigned num_slices;
+ unsigned l3_banks;
unsigned max_vs_threads; /**< Maximum Vertex Shader threads */
unsigned max_tcs_threads; /**< Maximum Hull Shader threads */
unsigned max_tes_threads; /**< Maximum Domain Shader threads */
diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index 0783217..4fe3503 100644
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -116,6 +116,7 @@ get_l3_configs(const struct gen_device_info *devinfo)
return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
case 9:
+ case 10:
return chv_l3_configs;
default:
diff --git a/src/intel/compiler/brw_compiler.h
b/src/intel/compiler/brw_compiler.h
index 9228413..98cd174 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -1021,7 +1021,7 @@ brw_stage_has_packed_dispatch(const struct
gen_device_info *devinfo,
* to do a full test run with brw_fs_test_dispatch_packing() hooked up to
* the NIR front-end before changing this assertion.
*/
- assert(devinfo->gen <= 9);
+ assert(devinfo->gen <= 10);
switch (stage) {
case MESA_SHADER_FRAGMENT: {
diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index 77400c1..2c0dc27 100644
--- a/src/intel/compiler/brw_eu.c
+++ b/src/intel/compiler/brw_eu.c
@@ -412,6 +412,7 @@ enum gen {
GEN75 = (1 << 5),
GEN8 = (1 << 6),
GEN9 = (1 << 7),
+ GEN10 = (1 << 8),
GEN_ALL = ~0
};
@@ -688,6 +689,7 @@ gen_from_devinfo(const struct gen_device_info *devinfo)
case 7: return devinfo->is_haswell ? GEN75 : GEN7;
case 8: return GEN8;
case 9: return GEN9;
+ case 10: return GEN10;
default:
unreachable("not reached");
}
diff --git a/src/intel/compiler/brw_eu_compact.c
b/src/intel/compiler/brw_eu_compact.c
index b2af76d..740a395 100644
--- a/src/intel/compiler/brw_eu_compact.c
+++ b/src/intel/compiler/brw_eu_compact.c
@@ -1362,6 +1362,7 @@ brw_init_compaction_tables(const struct gen_device_info
*devinfo)
assert(gen8_src_index_table[ARRAY_SIZE(gen8_src_index_table) - 1] != 0);
switch (devinfo->gen) {
+ case 10:
case 9:
case 8:
control_index_table = gen8_control_index_table;
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index c7072d0..45f75c1 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1651,6 +1651,7 @@ isl_surf_fill_state_s(const struct isl_device *dev, void
*state,
isl_gen8_surf_fill_state_s(dev, state, info);
break;
case 9:
+ case 10:
isl_gen9_surf_fill_state_s(dev, state, info);
break;
default:
@@ -1682,6 +1683,7 @@ isl_buffer_fill_state_s(const struct isl_device *dev,
void *state,
isl_gen8_buffer_fill_state_s(state, info);
break;
case 9:
+ case 10:
isl_gen9_buffer_fill_state_s(state, info);
break;
default:
diff --git a/src/intel/vulkan/anv_cmd_buffer.c
b/src/intel/vulkan/anv_cmd_buffer.c
index c65eba2..75d2a2e 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -334,6 +334,7 @@ anv_cmd_buffer_emit_state_base_address(struct
anv_cmd_buffer *cmd_buffer)
case 8:
return gen8_cmd_buffer_emit_state_base_address(cmd_buffer);
case 9:
+ case 10:
return gen9_cmd_buffer_emit_state_base_address(cmd_buffer);
default:
unreachable("unsupported gen\n");
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 4e4fa19..f2d5b8c 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1074,6 +1074,7 @@ VkResult anv_CreateDevice(
result = gen8_init_device_state(device);
break;
case 9:
+ case 10:
result = gen9_init_device_state(device);
break;
default:
diff --git a/src/intel/vulkan/anv_entrypoints_gen.py
b/src/intel/vulkan/anv_entrypoints_gen.py
index 203df45..594a8f4 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -175,6 +175,7 @@ TEMPLATE_C = Template(textwrap.dedent(u"""\
}
switch (devinfo->gen) {
+ case 10:
case 9:
if (gen9_layer.entrypoints[index])
return gen9_layer.entrypoints[index];
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index b69cb4f..8a6cc66 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -94,6 +94,7 @@ brw_blorp_init(struct brw_context *brw)
brw->blorp.exec = gen8_blorp_exec;
break;
case 9:
+ case 10:
brw->blorp.mocs.tex = SKL_MOCS_WB;
brw->blorp.mocs.rb = SKL_MOCS_PTE;
brw->blorp.mocs.vb = SKL_MOCS_WB;
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 025da5e..8554197 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -825,6 +825,7 @@ brw_emit_vertex_buffer_state(struct brw_context *brw,
dw0 |= BDW_MOCS_WB << 16;
break;
case 9:
+ case 10:
dw0 |= SKL_MOCS_WB << 16;
break;
}
diff --git a/src/mesa/drivers/dri/i965/brw_formatquery.c
b/src/mesa/drivers/dri/i965/brw_formatquery.c
index 96cc6e0..5faf91f 100644
--- a/src/mesa/drivers/dri/i965/brw_formatquery.c
+++ b/src/mesa/drivers/dri/i965/brw_formatquery.c
@@ -37,6 +37,7 @@ brw_query_samples_for_format(struct gl_context *ctx, GLenum
target,
(void) internalFormat;
switch (brw->gen) {
+ case 10:
case 9:
samples[0] = 16;
samples[1] = 8;
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index 811a9c5..4739197 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1615,6 +1615,7 @@ set_max_gl_versions(struct intel_screen *screen)
const bool has_astc = screen->devinfo.gen >= 9;
switch (screen->devinfo.gen) {
+ case 10:
case 9:
case 8:
dri_screen->max_gl_core_version = 45;
--
2.9.3
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