From: Ben Widawsky <benjamin.widaw...@intel.com>
GEN10 requires flushing all previous pipe controls before issuing a render
target cache flush. The docs seem to fairly explicitly say this is gen10 only.
v2: Rebased on
commit 04f74d66293222d5e1905cfb930bfa083e30463c
Author: Francisco Jerez <curroje...@riseup.net>
Date: Thu Jun 30 19:39:24 2016 -0700
i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.
Cc: Francisco Jerez <curroje...@riseup.net>
Signed-off-by: Ben Widawsky <benjamin.widaw...@intel.com>
---
src/mesa/drivers/dri/i965/brw_pipe_control.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index b8f7406..b921fe7 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -128,6 +128,24 @@ brw_emit_pipe_control_flush(struct brw_context *brw,
uint32_t flags)
brw_emit_pipe_control_flush(brw, 0);
}
+ if (brw->gen == 10) {
+ /* Hardware workaround: CNL
+ *
+ * "Before sending a PIPE_CONTROL command with bit 12 set, SW
+ * must issue another PIPE_CONTROL with Render Target Cache
+ * Flush Enable (bit 12) = 0 and Pipe Control Flush Enable (bit
+ * 7) = 1."
+ */
+ BEGIN_BATCH(6);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
+ OUT_BATCH(PIPE_CONTROL_FLUSH_ENABLE);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+ }
+
BEGIN_BATCH(6);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
OUT_BATCH(flags);
--
2.9.3
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