On Wed, 2016-05-11 at 12:05 -0700, Francisco Jerez wrote:
> Iago Toral writes:
>
> > On Wed, 2016-05-11 at 12:49 +0200, Iago Toral wrote:
> >> On Tue, 2016-05-10 at 19:10 -0700, Francisco Jerez wrote:
> >> > Samuel Iglesias Gonsálvez writes:
> >> >
> >> > > From: Iago Toral Quiroga
> >> > >
>
Hi,
I'm not sure if that answers your need, but to me it looks like
it would be simpler if gbm was trying different backends for the given
device, until it succeeds. You'd pass several backends to GBM_BACKEND
(perhaps
rename to GBM_BACKENDS), and in your example it would put amdgpu pro first.
T
On Wed, May 11, 2016 at 11:23:10PM -0700, Kenneth Graunke wrote:
> On Thursday, May 12, 2016 8:50:33 AM PDT Topi Pohjolainen wrote:
> > This hasn't been visible before. It showed up with lossless
> > compression with:
> >
> > dEQP-GLES3.functional.fbo.color.repeated_clear.sample.tex2d.rgb8
> >
>
On Thursday, May 12, 2016 8:50:33 AM PDT Topi Pohjolainen wrote:
> This hasn't been visible before. It showed up with lossless
> compression with:
>
> dEQP-GLES3.functional.fbo.color.repeated_clear.sample.tex2d.rgb8
>
> Current fast clear logic kicks color resolves even for gpu sampling.
> In the
Another comment:
What would solve your DRI_PRIME issues would also be
dma-buf fences.
While I believe thread_submit should be a bit better (because
it avoids a card stall waiting for another card to finish), dma-buf
fences make the two cards synchronize rendering properly.
I don't know much of
This hasn't been visible before. It showed up with lossless
compression with:
dEQP-GLES3.functional.fbo.color.repeated_clear.sample.tex2d.rgb8
Current fast clear logic kicks color resolves even for gpu sampling.
In the test case this results into trashing of the fast color clear
state between two
On 12/05/2016 04:41, Mike Lothian wrote:
Hi Axel
Is the thread_submit=true only for nine or does it work with all of DRI3?
I'm keen to get rid of the tearing on my Skylake/Tonga setup
Thanks
Mike
It is gallium nine only for now.
In the case of gallium nine, it as a reasonnable assumption
On 11/05/16 22:46, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> On Tue, 2016-05-10 at 21:06 -0700, Francisco Jerez wrote:
>>> Samuel Iglesias Gonsálvez writes:
>>>
From: Iago Toral Quiroga
UNIFORM_PULL_CONSTANT_LOAD is used to load a contiguous vec4
On 11/05/16 22:30, Francisco Jerez wrote:
> Samuel Iglesias Gonsálvez writes:
>
>> On 11/05/16 05:56, Francisco Jerez wrote:
>>> Samuel Iglesias Gonsálvez writes:
>>>
From: Connor Abbott
v2 (Iago)
- Fixup accessibility in backend_reg
Signed-off-by: Iago Toral Q
Francisco Jerez writes:
> Iago Toral writes:
>
>> On Tue, 2016-05-10 at 19:10 -0700, Francisco Jerez wrote:
>>> Samuel Iglesias Gonsálvez writes:
>>>
>>> > From: Iago Toral Quiroga
>>> >
>>> > There are a few places where we need to shuffle the result of a 32-bit
>>> > load
>>> > into valid
On Wed, May 11, 2016 at 12:22:37PM -0700, Kristian H?gsberg wrote:
> From: Kristian Høgsberg Kristensen
>
> This factors out the work of setting up a miptree as the backing for a
> texture image into a new helper.
> ---
> src/mesa/drivers/dri/i965/intel_tex_image.c | 69
> ++
Hi guys,
Let me introduce myself. My name is Qiang Yu, I'm a developer of amdgpu-pro
driver.
As you know the amdgpu-pro adopts some open source part like GBM but due to its
close source OGL part, we implement our own GBM backend.
Currently libgbm only support static selection of GBM backend
On Wed, May 11, 2016 at 10:42 PM, Jason Ekstrand wrote:
> The current MSAA resolve code has a special-case for if the MCS value is 0.
> In this case we can only sample once because we know that all values are in
> slice 0. This commit adds a second optimization that detecs the magic MCS
> value t
The current MSAA resolve code has a special-case for if the MCS value is 0.
In this case we can only sample once because we know that all values are in
slice 0. This commit adds a second optimization that detecs the magic MCS
value that indicates the clear color and grabs the color from a push
con
Hi Axel
Is the thread_submit=true only for nine or does it work with all of DRI3?
I'm keen to get rid of the tearing on my Skylake/Tonga setup
Thanks
Mike
On Wed, 11 May 2016 at 16:57 Axel Davy wrote:
> Hi,
>
> Do you have some local branch to review all at once (it is a bit hard to
> follow
https://bugs.freedesktop.org/show_bug.cgi?id=95346
--- Comment #8 from Ilia Mirkin ---
First bad draw call in the referenced trace is 803513, I believe. That ends up
with the "bad" earth - the S3TC texture of the earth doesn't appear to be
making it on there.
--
You are receiving this mail beca
Hi Axel,
Just clarify something you might got misunderstand on vl implementation
perspective.
>The present extension has something exactly to set the target ust for
the presentation: PresentOptionUST
>Unfortunately, while it is in the spec it looks like the option is
totally ignored, and t
https://bugs.freedesktop.org/show_bug.cgi?id=95346
--- Comment #7 from Ilia Mirkin ---
Replaying on nvc0 also brings up the same issue. So the current status is
llvmpipe: fail
nvc0: fail
radeonsi: fail (i assume, otherwise we wouldn't have this bug)
i965/SKL: success
Feels like a Gallium issue.
https://bugs.freedesktop.org/show_bug.cgi?id=95346
--- Comment #6 from Michel Dänzer ---
(In reply to Christopher W. Carpenter from comment #4)
> I'm not sure if this changes anything as far as assigning it to mesa core,
> but my laptop running the i915 driver with mesa 11.1.3 does not exhibit th
From: Ian Romanick
Watch the oes_shader_io_blocks of my fd.o Mesa GIT repo for progress.
Signed-off-by: Ian Romanick
---
docs/GL3.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index e2dabea..dce6421 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.
https://bugs.freedesktop.org/show_bug.cgi?id=95346
Médéric Boquien changed:
What|Removed |Added
CC||mboqu...@free.fr
--
You are receiving
In lieu of GL3.txt being updated, is there some way for me to get an
idea about what OpenSWR supports without digging through the code /
building tests?
FWIW, as an outsider I use mesamatrix to get a very nice overview on
what the different renderers support. I consider that valuable.
On Wed, May
I need to recind this patch. I thought it worked but it's far more
half-baked than I realized. There's some issue with swizzles interacting
with the clear color. :-(
--Jason
On Tue, May 10, 2016 at 9:45 PM, Jason Ekstrand
wrote:
> The current MSAA resolve code has a special-case for if the MCS
https://people.freedesktop.org/~imirkin/glxinfo/glxinfo.html
When swr makes it into a release, I'll be sure to add it in. This
shows what extensions each hardware group has. Note that this isn't
necessarily 1:1 with driver - a single driver might support several
iterations of hardware, and provide
Typically, if you expose the cap bits so that support for some extension
is announced you'd consider it done.
That does not necessarily mean that all the corresponding piglit tests
are passing, but of course you should generally not announce support for
features which don't really work (but you mig
Signed-off-by: Jordan Justen
---
src/intel/vulkan/Makefile.sources | 4 +
src/intel/vulkan/anv_genX.h| 4 +-
src/intel/vulkan/anv_pipeline.c| 33 ++-
src/intel/vulkan/anv_private.h | 12 +-
src/intel/vulkan/gen7_cmd_buffer.c | 94 +--
src/intel/vulkan/gen8_cmd_buffer.c
These were added to the i965 driver in
5912da45a69923afa1b7f2eb5bb371d848813c41.
Signed-off-by: Jordan Justen
---
src/intel/genxml/gen75.xml | 8
1 file changed, 8 insertions(+)
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 698d93f..2258dee 100644
--- a/src
If images or shader buffers are used, we will enable the data cache in
the the L3 config.
Signed-off-by: Jordan Justen
---
src/intel/vulkan/anv_pipeline.c | 8 +++-
src/intel/vulkan/anv_private.h | 1 +
src/intel/vulkan/genX_pipeline.c | 2 ++
3 files changed, 10 insertions(+), 1 deletion
We also have this barrier call for gen8 vkCmdWaitEvents.
We don't implement waiting on events for gen7 yet, but this barrier at
least helps to not regress CTS cases when data caching is enabled.
Without this, the tests would intermittently report a failure when the
data cache was enabled.
Signed-
git://people.freedesktop.org/~jljusten/mesa anv-l3-v1
This series is related to this bug:
https://bugs.freedesktop.org/show_bug.cgi?id=94468
Since we have a work-around for that bug currently, this doesn't fix
it. It does allow us to remove the work-around though.
Running through jenkins, I see
From: Jordan Justen
This reverts commit 41af9b2e517dd0c17e519490ca915b96f6898390.
---
src/intel/vulkan/genX_cmd_buffer.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index daa1884..b7c93bd 100644
--- a/sr
For patches 1-9:
Reviewed-by: Marek Olšák
Marek
On Tue, May 10, 2016 at 1:21 AM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> ---
> src/gallium/drivers/r300/r300_blit.c | 2 +-
> src/gallium/drivers/r300/r300_render.c| 2 +-
> src/gallium/drivers/r600/r600_hw_context.c
On Wed, May 11, 2016 at 2:16 PM, Kenneth Graunke
wrote:
> On Wednesday, May 11, 2016 12:16:41 PM PDT Jason Ekstrand wrote:
> > Is there a reason this never got merged? I'm up for just landing it now
> > and letting people fix up names as needed.
> > --Jason
>
> Sounds good to me. Jason, why don
On 05/11/2016 05:37 PM, Axel Davy wrote:
On 11/05/2016 23:31, Leo Liu wrote:
On 05/11/2016 05:18 PM, Axel Davy wrote:
On 11/05/2016 23:08, Leo Liu wrote:
scrn->next_msc = ((int64_t)stamp - scrn->last_ust +
scrn->ns_frame/2) /
+ scrn->ns_frame + scrn->last_msc;
Coul
On 11/05/2016 23:31, Leo Liu wrote:
On 05/11/2016 05:18 PM, Axel Davy wrote:
On 11/05/2016 23:08, Leo Liu wrote:
scrn->next_msc = ((int64_t)stamp - scrn->last_ust + scrn->ns_frame/2) /
+ scrn->ns_frame + scrn->last_msc;
Could you explain this calculation ?
ns_frame i
On 05/11/2016 05:18 PM, Axel Davy wrote:
On 11/05/2016 23:08, Leo Liu wrote:
scrn->next_msc = ((int64_t)stamp - scrn->last_ust + scrn->ns_frame/2) /
+ scrn->ns_frame + scrn->last_msc;
Could you explain this calculation ?
ns_frame is the time for vsync in ns.
last_ust
On Tue, May 10, 2016 at 1:21 AM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> ---
> src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 11 +++
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
> b/src/gallium/winsys/amdgpu/drm/amdg
On 11/05/2016 23:08, Leo Liu wrote:
scrn->next_msc = ((int64_t)stamp - scrn->last_ust + scrn->ns_frame/2) /
+ scrn->ns_frame + scrn->last_msc;
Could you explain this calculation ?
I think it may get issues if ns_frame is wrong. For example for some
reason (app hidden fo
On Wednesday, May 11, 2016 12:16:41 PM PDT Jason Ekstrand wrote:
> Is there a reason this never got merged? I'm up for just landing it now
> and letting people fix up names as needed.
> --Jason
Sounds good to me. Jason, why don't you go ahead and push it then?
--Ken
signature.asc
Description:
On 05/11/2016 04:20 PM, Axel Davy wrote:
On 11/05/2016 17:06, Leo Liu wrote:
Screen created with device fd returned from X server,
also will bail out to DRI2 with certain conditions.
Signed-off-by: Leo Liu
---
configure.ac | 7 ++-
src/gallium/auxiliary/vl/vl
On 05/11/2016 04:16 PM, Axel Davy wrote:
Hi,
The present extension has something exactly to set the target ust for
the presentation: PresentOptionUST
Unfortunately, while it is in the spec it looks like the option is
totally ignored, and thus it will be totally buggy (you are supposed
to
Samuel Iglesias Gonsálvez writes:
> On Tue, 2016-05-10 at 21:06 -0700, Francisco Jerez wrote:
>> Samuel Iglesias Gonsálvez writes:
>>
>> >
>> > From: Iago Toral Quiroga
>> >
>> > UNIFORM_PULL_CONSTANT_LOAD is used to load a contiguous vec4
>> > starting at a
>> > constant offset that is 16-b
https://bugs.freedesktop.org/show_bug.cgi?id=95346
--- Comment #5 from Ilia Mirkin ---
The trace replays fine on i965 (SKL) but incorrectly on llvmpipe, at commit
2655265 as well as on 11.2.2.
BTW, those "used uninitialized warnings" are hardly always accurate. They can
refer to dead code, etc.
Working my way through the python took some time as I'm not that
familiar with python either, but the series is
Reviewed-by: Bas Nieuwenhuizen
Also thanks for removing the designated array initializers.
- Bas
On Wed, May 11, 2016 at 10:13 PM, Marek Olšák wrote:
> For the series:
>
> Reviewed-
With this change, to enable precise SIN and COS instructions
on Intel hardware, one can put
in the proper drirc file.
V2: Make option name more generic
---
src/mesa/drivers/dri/common/xmlpool/t_options.h | 5 +
src/mesa/drivers/dri/i965/brw_compiler.c| 2 --
src/mesa/drivers/dri/i9
Samuel Iglesias Gonsálvez writes:
> On 11/05/16 05:56, Francisco Jerez wrote:
>> Samuel Iglesias Gonsálvez writes:
>>
>>> From: Connor Abbott
>>>
>>> v2 (Iago)
>>> - Fixup accessibility in backend_reg
>>>
>>> Signed-off-by: Iago Toral Quiroga
>>
>> I've just noticed (while running valgrind
On 11/05/2016 17:06, Leo Liu wrote:
Screen created with device fd returned from X server,
also will bail out to DRI2 with certain conditions.
Signed-off-by: Leo Liu
---
configure.ac | 7 ++-
src/gallium/auxiliary/vl/vl_winsys_dri3.c | 88
Hi,
The present extension has something exactly to set the target ust for
the presentation: PresentOptionUST
Unfortunately, while it is in the spec it looks like the option is
totally ignored, and thus it will be totally buggy (you are supposed to
pass ust instead of msc...).
However Prese
For the series:
Reviewed-by: Marek Olšák
Except patch 6, which is:
Acked-by: Marek Olšák
It's just too much python for me and I don't consider myself a python guy.
Marek
On Mon, May 9, 2016 at 6:32 PM, Nicolai Hähnle wrote:
> From: Nicolai Hähnle
>
> This is purely cosmetic, making it ea
Samuel Iglesias Gonsálvez writes:
> On Wed, 2016-05-11 at 17:12 +0200, Samuel Iglesias Gonsálvez wrote:
>> On Tue, 2016-05-10 at 21:06 -0700, Francisco Jerez wrote:
>> >
>> > Samuel Iglesias Gonsálvez writes:
>> >
>> > >
>> > >
>> > > From: Iago Toral Quiroga
>> > >
>> > > UNIFORM_PULL_CON
On Wednesday, May 11, 2016 1:19:01 PM PDT Juan A. Suarez Romero wrote:
> On Fri, 2016-04-29 at 14:23 +0200, Juan A. Suarez Romero wrote:
> > On Fri, 2016-04-29 at 11:15 +0200, Ian Romanick wrote:
> > >
> > > The driver supports up to 16 vertex attributes.
> > > >
> > > > ARB_vertex_attrib_64bit
>
Iago Toral writes:
> On Tue, 2016-05-10 at 19:10 -0700, Francisco Jerez wrote:
>> Samuel Iglesias Gonsálvez writes:
>>
>> > From: Iago Toral Quiroga
>> >
>> > There are a few places where we need to shuffle the result of a 32-bit load
>> > into valid 64-bit data, so extract this logic into a s
From: Kristian Høgsberg Kristensen
This will be used to select the plane to sample from for planar
textures.
Reviewed-by: Jason Ekstrand
---
src/compiler/nir/nir.h | 1 +
src/compiler/nir/nir_print.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/co
Iago Toral writes:
> On Tue, 2016-05-10 at 19:10 -0700, Francisco Jerez wrote:
>> Samuel Iglesias Gonsálvez writes:
>>
>> > From: Iago Toral Quiroga
>> >
>> > There are a few places where we need to shuffle the result of a 32-bit load
>> > into valid 64-bit data, so extract this logic into a s
From: Kristian Høgsberg Kristensen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 +++
src/mesa/drivers/dri/i965/intel_tex_image.c | 49 ++-
src/mesa/drivers/dri/i965/intel_tex_obj.h | 2 ++
4 files cha
From: Kristian Høgsberg Kristensen
This lowers sampling from YUV textures to 1) one or more texture
instructions to sample each plane and 2) color space conversion to RGB.
Reviewed-by: Jason Ekstrand
---
src/compiler/nir/nir.h | 7 +++
src/compiler/nir/nir_lower_tex.c | 119 ++
From: Kristian Høgsberg Kristensen
This factors out the work of setting up a miptree as the backing for a
texture image into a new helper.
---
src/mesa/drivers/dri/i965/intel_tex_image.c | 69 ++---
1 file changed, 42 insertions(+), 27 deletions(-)
diff --git a/src/mesa/
From: Kristian Høgsberg Kristensen
Reviewed-by: Jason Ekstrand
---
src/compiler/nir/nir.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index 867a43c..f15c993 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -642,6 +64
From: Kristian Høgsberg Kristensen
---
include/GL/internal/dri_interface.h | 5 +
src/mesa/drivers/dri/i965/intel_screen.c | 26 ++
2 files changed, 31 insertions(+)
diff --git a/include/GL/internal/dri_interface.h
b/include/GL/internal/dri_interface.h
index 8
From: Kristian Høgsberg Kristensen
---
src/mesa/drivers/dri/i965/brw_compiler.h | 7 +++
src/mesa/drivers/dri/i965/brw_nir.c | 4
src/mesa/drivers/dri/i965/brw_wm.c | 29 +
3 files changed, 40 insertions(+)
diff --git a/src/mesa/drivers/dri/i965
From: Kristian Høgsberg Kristensen
Create the mt for the drawable bo directly and call our new
intel_miptree_create_for_bo() helper instead.
---
src/mesa/drivers/dri/i965/intel_tex_image.c | 27 +++
1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/src/mesa/
From: Kristian Høgsberg Kristensen
---
src/mesa/drivers/dri/i965/brw_compiler.h | 1 +
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 13
src/mesa/drivers/dri/i965/brw_shader.cpp | 9 ++
src/mesa/dri
From: Kristian Høgsberg Kristensen
Here's v2 of the series. Incorporates Topi's and Jason comments, but
also refactors the miptree creation a bit. The old series broke
support for certain EGLImages (images without a planar_format), but
they're now working as they did before.
Kristian
Kristian H
From: Kristian Høgsberg Kristensen
Lift the resctriction we had before and allow creation of images with
multiple planes. We still require all the planes to be within the same
bo.
---
src/mesa/drivers/dri/i965/intel_screen.c | 33 ++--
1 file changed, 19 insertions(+)
From: Kristian Høgsberg Kristensen
This function now only creates the mt and we then call
intel_set_texture_image_mt() in intel_image_target_texture_2d() to set
it for the texture image.
---
src/mesa/drivers/dri/i965/intel_tex_image.c | 69 +
1 file changed, 30 insert
>> + whandle.type= DRM_API_HANDLE_TYPE_FD;
>> + usage = PIPE_HANDLE_USAGE_EXPLICIT_FLUSH | PIPE_HANDLE_USAGE_READ;
>Here using
>PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
> is wrong. Both vaapi and vdpau don't call flush_resource.
>Perhaps vaapi and vdpau can get fixed to call it, I don't know which
yes please.. scripts/get_reviewer.pl should in theory respect this
too, so useful to have
BR,
-R
On Wed, May 11, 2016 at 3:16 PM, Jason Ekstrand wrote:
> Is there a reason this never got merged? I'm up for just landing it now and
> letting people fix up names as needed.
> --Jason
>
> On Mon, D
On Wed, May 11, 2016 at 12:09 PM, Rob Clark wrote:
> From: Rob Clark
>
> It's what all the call-sites once, so gets rid of a bunch of inlined
> glsl_get_base_type() at the call-sites.
>
Thank you! This has been bothering me for a while. At some point in the
future, a glsl_get_base_type_bit_si
Is there a reason this never got merged? I'm up for just landing it now
and letting people fix up names as needed.
--Jason
On Mon, Dec 28, 2015 at 1:50 AM, Giuseppe Bilotta <
giuseppe.bilo...@gmail.com> wrote:
> This adds a first tentative .mailmap file, to canonicize contributor
> name/emails i
From: Rob Clark
It's what all the call-sites once, so gets rid of a bunch of inlined
glsl_get_base_type() at the call-sites.
Signed-off-by: Rob Clark
---
Plus, for mediump, going to need glsl_get_base_type() to take a
precision param.. this should make it less of a challenge to stay
in 80 colum
Iago Toral writes:
> On Wed, 2016-05-11 at 12:49 +0200, Iago Toral wrote:
>> On Tue, 2016-05-10 at 19:10 -0700, Francisco Jerez wrote:
>> > Samuel Iglesias Gonsálvez writes:
>> >
>> > > From: Iago Toral Quiroga
>> > >
>> > > There are a few places where we need to shuffle the result of a 32-bi
https://bugs.freedesktop.org/show_bug.cgi?id=95354
Mark Janes changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
Iago Toral writes:
> On Tue, 2016-05-10 at 16:53 -0700, Francisco Jerez wrote:
>> Samuel Iglesias Gonsálvez writes:
>>
>> > From: Iago Toral Quiroga
>> >
>> > We were not accounting for reg_suboffset in the check for the start
>> > of the region. This meant that would allow copy-propagation ev
In the GLX dispatch functions, it should be safe to ignore a failed call
to AddDrawableMapping. If it can't update the drawable-to-vendor
hashtable at that point, then libGLX will just query the server when it
needs to figure out the vendor.
In dispatch_ChooseFBConfigSGIX, if AddFBConfigsMappi
Again another comment for the same patch:
vl_dri3_screen_texture_from_drawable seem to call dri3_get_back_buffer
in the !is_pixmap case.
If I understand dri3_get_back_buffer will puck an idle buffer of the
buffer list.
Is it really what is expected ?
Shouldn't vl_dri3_screen_texture_from_dr
Iago Toral writes:
> On Tue, 2016-05-10 at 16:53 -0700, Francisco Jerez wrote:
>> Samuel Iglesias Gonsálvez writes:
>>
>> > From: Iago Toral Quiroga
>> >
>> > We were not accounting for reg_suboffset in the check for the start
>> > of the region. This meant that would allow copy-propagation ev
Another thing is that I think there is no guarantee the Xserver releases
all the pixmaps,
and that it could keep one infinitely (until window destruction).
Thus if the drawable is changed by the user, but the previous drawable
isn't destroyed by the user,
one buffer can stay busy forever. Chang
On Wed, May 11, 2016 at 9:28 AM, Pohjolainen, Topi <
topi.pohjolai...@intel.com> wrote:
> On Tue, May 10, 2016 at 04:16:20PM -0700, Jason Ekstrand wrote:
> > When Paul originally wrote blorp he hand-rolled a shader builder that
> > builds i965 shaders directly. This has caused headaches because e
The helper was initially created to allow us to set reasonable defaults as
we mutated the brw_blorp_prog_data structure in preparation for NIR. Now
that everything is going through brw_blorp_compile_nir_shader() which fully
fills out the brw_blorp_prog_data structure, we don't need the helper.
---
On 11/05/2016 17:06, Leo Liu wrote:
This implements DRI3 PixmapFromBuffer. Create buffer objects, and
associate it to a dma-buf fd, and then pass this fd with a pixmap
ID to X server for creating pixmap object; also add a function
for wait events.
Signed-off-by: Leo Liu
---
src/gallium/auxili
Am 11.05.2016 um 17:06 schrieb Leo Liu:
This series implement DRI3 supports for VA-API and VDPAU. It implements
supports for DRI3 Open, PixmapFromBuffer, BufferFromPixmap, and for
PRESENT including PresentPixmap, PresentNotifyMSC, PresentIdleNotify,
PresentConfigureNotify and PresentCompleteNotif
On Wed, May 11, 2016 at 8:39 AM, Pohjolainen, Topi <
topi.pohjolai...@intel.com> wrote:
> On Wed, May 11, 2016 at 07:46:33AM -0700, Jason Ekstrand wrote:
> >On May 11, 2016 7:45 AM, "Jason Ekstrand" <[1]ja...@jlekstrand.net>
> >wrote:
> >>
> >>
> >> On May 10, 2016 11:53 PM, "P
On Tue, May 10, 2016 at 04:16:37PM -0700, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c | 95
> +++
> src/mesa/drivers/dri/i965/brw_blorp.h | 10
> 2 files changed, 105 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
From: Kyle Brenneman
With reference to the libglvnd branch:
https://cgit.freedesktop.org/mesa/mesa/log/?h=libglvnd
This is a squashed commit containing all of Kyle's commits, all but two
of Emil's commits (to follow), and a small fixup from myself to mark the
rest of the glX* functions as _GLX_
From: Emil Velikov
Rather than checking if the function name maps to a valid entry in the
respective table, just create a dummy entry at the end of each table.
This allows us to remove some unnessesary "index >= 0" checks, which get
executed quite often.
Reviewed-by: Adam Jackson
Signed-off-by
From: Emil Velikov
It will allows us to find the function within 6 attempts, out of the ~80
entry long table.
Reviewed-by: Adam Jackson
Signed-off-by: Emil Velikov
---
src/glx/glxglvnd.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/src/glx/glxglvnd.c
https://bugs.freedesktop.org/show_bug.cgi?id=95354
Bug ID: 95354
Summary: anv_pipeline.c:164:7: error: implicit declaration of
function ‘nir_lower_outputs_to_temporaries’
[-Werror=implicit-function-declaration]
Product: Mesa
On Wed, May 11, 2016 at 12:25 AM, Pohjolainen, Topi <
topi.pohjolai...@intel.com> wrote:
> On Tue, May 10, 2016 at 04:16:36PM -0700, Jason Ekstrand wrote:
> > ---
> > src/mesa/drivers/dri/i965/brw_blorp.c | 6 +-
> > src/mesa/drivers/dri/i965/brw_blorp.h | 8 +++-
> > sr
On Tue, May 10, 2016 at 04:16:35PM -0700, Jason Ekstrand wrote:
> This array allows the push constants to be re-arranged on upload. The
> actual arrangement will, eventually, come from the back-end compiler.
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c | 4
> src/mesa/drivers/dri/i965/brw
It is whatever you (i.e. driver maintainer) want it to be. GL3.txt is
mainly for coordinating development and letting people know who's
working on what (less so of late though). If you plan on exposing GL
4.0+, it can be a nice TODO list. Otherwise there's not an immense
amount of value.
-ilia
Hi Axel,
Thanks for the comments. Inlines.
On 05/11/2016 11:57 AM, Axel Davy wrote:
Hi,
Do you have some local branch to review all at once (it is a bit hard
to follow with the patches) ?
The sequences of patches are based on existing vl/dri required
functions, also follows vaapi and then
What is the criteria for marking an extension “done”? Passing some percentage
(all?) of relevant piglit tests?
-Tim
> On May 10, 2016, at 10:31 PM, Andrew J wrote:
>
> Is there any possibility that OpenSWR can be added to GL3.txt [1] so
> others can get an idea of what things OpenSWR supports
On Tue, May 10, 2016 at 04:16:20PM -0700, Jason Ekstrand wrote:
> When Paul originally wrote blorp he hand-rolled a shader builder that
> builds i965 shaders directly. This has caused headaches because every time
> we make a change to the back-end compiler, we have to update blorp. NIR on
> the o
Testing android-x86 with mesa 11.2.2,
I found the Google Play crashed forever on
a device with Intel Gen9 GPU (e.g., Skylake).
After analyzing, the i965 driver seems to assume
irb->mt is not null. For example in
brw_meta_fast_clear of brw_meta_fast_clear.c:
struct intel_renderbuffer *irb =
On Tue, May 10, 2016 at 3:43 PM, Emil Velikov wrote:
> On 9 May 2016 at 20:33, Rob Clark wrote:
>> From: Jose Fonseca
>>
>> Signed-off-by: Rob Clark
>> ---
>> src/compiler/SConscript | 57
>> +++--
>> 1 file changed, 55 insertions(+), 2 deletions(-)
Hi,
Do you have some local branch to review all at once (it is a bit hard to
follow with the patches) ?
From a quick looks, it seems you inspired from the loader dri3 code.
There is also another implementation you can inspire from:
https://github.com/iXit/wine/blob/master/dlls/d3d9-nine/dri3.
On Wed, May 11, 2016 at 11:06 AM, Leo Liu wrote:
> This series implement DRI3 supports for VA-API and VDPAU. It implements
> supports for DRI3 Open, PixmapFromBuffer, BufferFromPixmap, and for
> PRESENT including PresentPixmap, PresentNotifyMSC, PresentIdleNotify,
> PresentConfigureNotify and Pres
On Wed, May 11, 2016 at 07:46:33AM -0700, Jason Ekstrand wrote:
>On May 11, 2016 7:45 AM, "Jason Ekstrand" <[1]ja...@jlekstrand.net>
>wrote:
>>
>>
>> On May 10, 2016 11:53 PM, "Pohjolainen, Topi"
><[2]topi.pohjolai...@intel.com> wrote:
>> >
>> > On Tue, May 10, 2016
On Wed, 2016-05-11 at 17:12 +0200, Samuel Iglesias Gonsálvez wrote:
> On Tue, 2016-05-10 at 21:06 -0700, Francisco Jerez wrote:
> >
> > Samuel Iglesias Gonsálvez writes:
> >
> > >
> > >
> > > From: Iago Toral Quiroga
> > >
> > > UNIFORM_PULL_CONSTANT_LOAD is used to load a contiguous vec4
>
This will clear presentation area not covered by video content
Signed-off-by: Leo Liu
---
src/gallium/auxiliary/vl/vl_winsys_dri3.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/gallium/auxiliary/vl/vl_winsys_dri3.c
b/src/gallium/auxiliary/vl/vl_winsys_dri3
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