Re: [Mesa-dev] [PATCH] i965: Correct constant buffer MOCS

On Tue, 02 Jun 2015 20:32:13 -0700 Kenneth Graunke wrote: > On Tuesday, June 02, 2015 08:07:50 PM Ben Widawsky wrote: > > I'm very confused here. It seems pretty clear that since the > > command has been introduced with support for MOCS, MOCS lives at > > bit 8 of dword 0 for all constant buffers

[Mesa-dev] [Bug 90797] [ALL bisected] Mesa change cause performance case manhattan fail.

https://bugs.freedesktop.org/show_bug.cgi?id=90797 wendy.w...@intel.com changed: What|Removed |Added Summary|[SKL bisected] Mesa change |[ALL bisected] Mesa change

Re: [Mesa-dev] [PATCH] i965/fs: Print mlen in dump_instructions() output.

Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] i965/fs: Print mlen in dump_instructions() output.

Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_fs.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 28a19bd..902f239 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drive

Re: [Mesa-dev] [PATCH] i965: Set max texture buffer size to hardware limit

On Wednesday, June 03, 2015 12:22:43 PM Chris Forbes wrote: > Previously we were leaving this at the default of 64K, which meets the > spec but is too small for some real uses. The hardware can handle up to > 128M. > > User was complaining about this on freenode ##OpenGL today. > > Signed-off-by:

Re: [Mesa-dev] [PATCH] i965: Correct constant buffer MOCS

On Tuesday, June 02, 2015 08:07:50 PM Ben Widawsky wrote: > I'm very confused here. It seems pretty clear that since the command has been > introduced with support for MOCS, MOCS lives at bit 8 of dword 0 for all > constant buffers. The error has existed since forever AFAICT. > > No piglit regress

[Mesa-dev] [PATCH] i965: Correct constant buffer MOCS

I'm very confused here. It seems pretty clear that since the command has been introduced with support for MOCS, MOCS lives at bit 8 of dword 0 for all constant buffers. The error has existed since forever AFAICT. No piglit regressions or fixes: http://otc-mesa-ci.jf.intel.com/view/dev/job/bwidawsk

Re: [Mesa-dev] [PATCH] i965/fs: Use UW-typed immediate in multiply inst.

After discussion on IRC, this seems reasonable to me. Unfortunate that CHV is fussy. Reviewed-by: Chris Forbes On Wed, Jun 3, 2015 at 1:24 PM, Matt Turner wrote: > Some hardware reads only the low 16-bits even if the type is UD, but > other hardware like Cherryview can't handle this. > > Fixes

[Mesa-dev] [PATCH] i965/fs: Use UW-typed immediate in multiply inst.

Some hardware reads only the low 16-bits even if the type is UD, but other hardware like Cherryview can't handle this. Fixes spec@arb_gpu_shader5@execution@sampler_array_indexing@fs-simple on Cherryview. --- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +- 1 file changed, 1 insertion(+), 1

Re: [Mesa-dev] [PATCH] i965: Set max texture buffer size to hardware limit

On Tue, Jun 2, 2015 at 5:22 PM, Chris Forbes wrote: > Previously we were leaving this at the default of 64K, which meets the > spec but is too small for some real uses. The hardware can handle up to > 128M. > > User was complaining about this on freenode ##OpenGL today. Does he know that we're on

[Mesa-dev] [PATCH] i965: Set max texture buffer size to hardware limit

Previously we were leaving this at the default of 64K, which meets the spec but is too small for some real uses. The hardware can handle up to 128M. User was complaining about this on freenode ##OpenGL today. Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_context.c | 1 + 1 file

[Mesa-dev] [PATCH V3 21/22] i965/gen9: Plugin the code for selecting YF/YS tiling on skl+

Buffers with Yf/Ys tiling end up using meta upload / download paths or the blitter for cases where they used tiled_memcpy paths in case of Y tiling. This has exposed some bugs in meta path. To avoid any piglit regressions on SKL this patch keeps the Yf/Ys tiling disabled at the moment. V3: Make br

[Mesa-dev] [PATCH] llvmpipe: Implement stencil export

From: Roland Scheidegger Pretty trivial, fixes the issue that we're expected to be able to blit stencil surfaces (as the blit just relies on util blitter code which needs stencil export to do it). 2 piglits skip->pass, 11 fail->pass v2: prettify, keep different stencil ref value handling out of

Re: [Mesa-dev] [PATCH] llvmpipe: Implement stencil export

On 3 June 2015 at 05:52, wrote: > From: Roland Scheidegger Looks good to me, Reviewed-by: Dave Airlie > > Pretty trivial, fixes the issue that we're expected to be able to blit > stencil surfaces (as the blit just relies on util blitter code which needs > stencil export to do it). > 2 piglits

Re: [Mesa-dev] [PATCH V3 17/22] i965/gen9: Add XY_FAST_COPY_BLT support to intelEmitCopyBlit()

On Tue, Jun 2, 2015 at 4:04 PM, Anuj Phogat wrote: > This patch enables using XY_FAST_COPY_BLT only for Yf/Ys tiled buffers. > It can be later turned on for other tiling patterns (X,Y) too. > > V3: Flush in between sequential fast copy blits. > Fix src/dst alignment requirements. > Make ca

[Mesa-dev] [PATCH V3 17/22] i965/gen9: Add XY_FAST_COPY_BLT support to intelEmitCopyBlit()

This patch enables using XY_FAST_COPY_BLT only for Yf/Ys tiled buffers. It can be later turned on for other tiling patterns (X,Y) too. V3: Flush in between sequential fast copy blits. Fix src/dst alignment requirements. Make can_fast_copy_blit() helper. Use ffs(), is_power_of_two()

[Mesa-dev] [PATCH 17.5/22] i965/skl: Extract the blit command setup in to a helper

Signed-off-by: Anuj Phogat Cc: Ben Widawsky --- Patch can be squashed with 17/22. I kept it separate for easy review. src/mesa/drivers/dri/i965/intel_blit.c | 93 ++ 1 file changed, 61 insertions(+), 32 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_b

[Mesa-dev] [PATCH V3 14/22] i965/gen9: Set vertical and horizontal surface alignments

Patch sets the alignments for texture and renderbuffer surfaces. V3: Make changes inside horizontal_alignment() and vertical_alignment() (Topi) Signed-off-by: Anuj Phogat Cc: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen8_surface_state.c | 32 +- 1 file changed

Re: [Mesa-dev] [RFC v2 08/15] mesa/formats: store whether or not a format is sRGB in gl_format_info

On Mon, Jun 1, 2015 at 10:13 AM, Nanley Chery wrote: > From: Nanley Chery > > v2: remove extra newline. > > Signed-off-by: Nanley Chery > --- > src/mesa/main/format_info.py | 2 ++ > src/mesa/main/formats.c | 28 > 2 files changed, 6 insertions(+), 24 deletion

Re: [Mesa-dev] [RFC v2 06/15] mesa/texcompress: enable translation between MESA and GL ASTC formats

On Mon, Jun 1, 2015 at 10:13 AM, Nanley Chery wrote: > From: Nanley Chery > > Signed-off-by: Nanley Chery > --- > src/mesa/main/texcompress.c | 114 > > 1 file changed, 114 insertions(+) > > diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/t

Re: [Mesa-dev] [RFC v2 04/15] mesa: add ASTC extensions to the extensions table

On Mon, Jun 1, 2015 at 10:13 AM, Nanley Chery wrote: > From: Nanley Chery > > v2: alphabetize the extensions. > remove OES ASTC extension. > > Signed-off-by: Nanley Chery > --- > src/mesa/main/extensions.c | 2 ++ > src/mesa/main/mtypes.h | 2 ++ > 2 files changed, 4 insertions(+) > > d

Re: [Mesa-dev] [RFC v2 05/15] mesa/glformats: recognize ASTC formats as compressed

On Mon, Jun 1, 2015 at 10:13 AM, Nanley Chery wrote: > From: Nanley Chery > > Signed-off-by: Nanley Chery > --- > src/mesa/main/glformats.c | 29 + > 1 file changed, 29 insertions(+) > > diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c > index 6a77c

Re: [Mesa-dev] [RFC v2 03/15] mesa: disable online compression for ASTC formats

On Mon, Jun 1, 2015 at 10:13 AM, Nanley Chery wrote: > From: Nanley Chery > > Signed-off-by: Nanley Chery > --- > src/mesa/main/texcompress.c | 22 ++ > src/mesa/main/teximage.c| 28 > 2 files changed, 50 insertions(+) > > diff --git a/src/me

[Mesa-dev] [RFC 0/3] implement nouveau-perfKit

Hello, A series I started a long time ago but now I need some feedbacks. :-) This state tracker implements NVIDIA PerfKit 3.0.1 which is currently only available on Windows 7+ for desktop graphics cards. A Linux/Android implementation is provided by NVIDIA but only for NVIDIA Tegra K1. This Gall

[Mesa-dev] [RFC 3/3] st/perfkit: add a state tracker for NVIDIA PerfKit

This state tracker implements NVIDIA PerfKit 3.0.1 which is currently only available on Windows 7+ for desktop graphics cards. A Linux/Android implementation is provided by NVIDIA but only for NVIDIA Tegra K1. This Gallium state tracker is loosely based on the VDPAU tracker and since it uses the p

[Mesa-dev] [RFC 2/3] util: add LIST_MOVE_TAIL to list.h

Signed-off-by: Samuel Pitoiset --- src/util/list.h | 9 + 1 file changed, 9 insertions(+) diff --git a/src/util/list.h b/src/util/list.h index fb566f5..c782ef5 100644 --- a/src/util/list.h +++ b/src/util/list.h @@ -116,12 +116,21 @@ static inline void list_validate(struct list_head *list

[Mesa-dev] [RFC 1/3] util: move LIST_FIRST_ENTRY from nv30_query.c to list.h

Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nv30/nv30_query.c | 3 --- src/util/list.h | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/nouveau/nv30/nv30_query.c b/src/gallium/drivers/nouveau/nv30/nv30_qu

Re: [Mesa-dev] [PATCH 1/6] draw: silence unused var warnings for non-debug build

On 06/01/2015 07:39 AM, Jose Fonseca wrote: On 01/06/15 14:20, Brian Paul wrote: --- src/gallium/auxiliary/draw/draw_llvm.c | 4 1 file changed, 4 insertions(+) diff --git a/src/gallium/auxiliary/draw/draw_llvm.c b/src/gallium/auxiliary/draw/draw_llvm.c index b9e55af..885c27c 100644 ---

[Mesa-dev] [PATCH] llvmpipe: Implement stencil export

From: Roland Scheidegger Pretty trivial, fixes the issue that we're expected to be able to blit stencil surfaces (as the blit just relies on util blitter code which needs stencil export to do it). 2 piglits skip->pass, 11 fail->pass --- src/gallium/drivers/llvmpipe/lp_bld_depth.c | 15 ++

Re: [Mesa-dev] [PATCH 3/3] program: Replace gl_inst_opcode with enum prog_opcode.

Series LGTM. Reviewed-by: Brian Paul On 06/02/2015 01:23 PM, Matt Turner wrote: Both were introduced at the same time. I'm not sure why we needed two. --- src/mesa/program/ir_to_mesa.cpp | 2 +- src/mesa/program/prog_instruction.c | 10 +- src/mesa/program/prog_instruction.h

[Mesa-dev] [PATCH 1/3] program: Shrink and rename SaturateMode field to Saturate.

It was 2 bits to accommodate SATURATE_PLUS_MINUS_ONE (removed by commit 09b566e1). A similar change was made to TGSI recently in commit e1c4e8aa. Reducing the size from 2 bits to 1 reduces the size of the bit fields from 17 bits to 16, which is a much nicer number. --- src/mesa/drivers/dri/i915/i

[Mesa-dev] [PATCH 2/3] program: Remove dead Aux field from prog_instruction.

Appears to have been last used by the i965 driver (removed by commit 098acf6c). --- src/mesa/program/prog_instruction.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/mesa/program/prog_instruction.h b/src/mesa/program/prog_instruction.h index 3ada857..3518f6c 100644 --- a/src/mesa/prog

[Mesa-dev] [PATCH 3/3] program: Replace gl_inst_opcode with enum prog_opcode.

Both were introduced at the same time. I'm not sure why we needed two. --- src/mesa/program/ir_to_mesa.cpp | 2 +- src/mesa/program/prog_instruction.c | 10 +- src/mesa/program/prog_instruction.h | 14 +++--- src/mesa/program/program_parse.y| 6 +++--- 4 files changed, 16

Re: [Mesa-dev] [PATCH V3 03/22] i965: Move intel_miptree_choose_tiling() to brw_tex_layout.c

On Tue, Jun 02, 2015 at 11:09:31AM -0700, Anuj Phogat wrote: > and change the name to brw_miptree_choose_tiling(). > > V3: Remove redundant function parameters. (Topi) > > Signed-off-by: Anuj Phogat > Reviewed-by: Topi Pohjolainen > --- > Comment made by Topi on patch 02/22 is fixed in V3 of th

Re: [Mesa-dev] [PATCH] i965/vec4: Fix the source register for indexed samplers

On Thu, May 28, 2015 at 11:35 AM, Neil Roberts wrote: > Previously when setting up the sample instruction for an indirect > sampler the vec4 backend was directly passing the pseudo opcode's > src0. However this isn't actually set to a valid register because > instead the MRF registers are used as

[Mesa-dev] [PATCH V3 03/22] i965: Move intel_miptree_choose_tiling() to brw_tex_layout.c

and change the name to brw_miptree_choose_tiling(). V3: Remove redundant function parameters. (Topi) Signed-off-by: Anuj Phogat Reviewed-by: Topi Pohjolainen --- Comment made by Topi on patch 02/22 is fixed in V3 of this patch. src/mesa/drivers/dri/i965/brw_tex_layout.c| 107 +

[Mesa-dev] Request for Mentorship

Hello, I am looking to participate in the X.org Evoc program this holiday and I wish to know if anyone is willing to mentor my Project . Looks like one of my potential mentors will not be predisposed to assis

Re: [Mesa-dev] [PATCH resend 7/7] i965: Disable HW-binding tables on batch finish for Broadwell

On Tuesday, June 02, 2015 03:23:35 PM Abdiel Janulgue wrote: > > On 06/02/2015 09:31 AM, Kenneth Graunke wrote: > > On Monday, June 01, 2015 03:14:30 PM Abdiel Janulgue wrote: > >> This is needed since kernel doesn't support RS context save and > >> restore on BDW yet. So manually disable hw-gener

Re: [Mesa-dev] [RFC v2 07/15] mesa/teximage: return the base internal format of the ASTC formats

On Mon, Jun 1, 2015 at 10:13 AM, Nanley Chery wrote: > From: Nanley Chery > > This is necesary to initialize the gl_texture_image struct. > > From the KHR_texture_compression_astc_ldr spec: > "Added to Section 3.8.6, Compressed Texture Images > >Add the tokens specified above to Table 3.16,

Re: [Mesa-dev] [PATCH] nir: prevent use-after-free condition in should_lower_phi()

Good work on finding this! Reviewed-by: Jason Ekstrand On Tue, Jun 2, 2015 at 4:42 AM, Eduardo Lima Mitev wrote: > lower_phis_to_scalar() pass recurses the instruction dependence graph to > determine if all the sources of a given instruction are scalarizable. > To prevent cycles, it temporary m

Re: [Mesa-dev] [PATCH 1/2] nir: remove extra semicolon

Reviewed-by: Jason Ekstrand On Tue, Jun 2, 2015 at 2:35 AM, Timothy Arceri wrote: > --- > src/glsl/nir/nir_lower_atomics.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/glsl/nir/nir_lower_atomics.c > b/src/glsl/nir/nir_lower_atomics.c > index f6f8902..0457de6 100

Re: [Mesa-dev] [PATCH 2/2] nir: use src for ssa helper

Both are Reviewed-by: Connor Abbott On Tue, Jun 2, 2015 at 5:37 AM, Timothy Arceri wrote: > --- > src/glsl/nir/glsl_to_nir.cpp | 5 + > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp > index af758ce..a471a86 10064

[Mesa-dev] [Bug 90817] swrast fails to load with certain remote X servers

https://bugs.freedesktop.org/show_bug.cgi?id=90817 Jon TURNEY changed: What|Removed |Added CC||jon.tur...@dronecode.org.uk -- You are rec

[Mesa-dev] [Bug 90817] swrast fails to load with certain remote X servers

https://bugs.freedesktop.org/show_bug.cgi?id=90817 --- Comment #3 from Tom Hughes --- Created attachment 116242 --> https://bugs.freedesktop.org/attachment.cgi?id=116242&action=edit Patch to loosen checking of visuals -- You are receiving this mail because: You are the QA Contact for the bug.

[Mesa-dev] [Bug 90817] swrast fails to load with certain remote X servers

https://bugs.freedesktop.org/show_bug.cgi?id=90817 --- Comment #4 from Tom Hughes --- Created attachment 116243 --> https://bugs.freedesktop.org/attachment.cgi?id=116243&action=edit Output of glxinfo run remotely with patch -- You are receiving this mail because: You are the QA Contact for th

[Mesa-dev] [Bug 90817] swrast fails to load with certain remote X servers

https://bugs.freedesktop.org/show_bug.cgi?id=90817 --- Comment #2 from Tom Hughes --- Created attachment 116241 --> https://bugs.freedesktop.org/attachment.cgi?id=116241&action=edit Output of glxinfo run remotely without patch -- You are receiving this mail because: You are the QA Contact for

[Mesa-dev] [Bug 90817] swrast fails to load with certain remote X servers

https://bugs.freedesktop.org/show_bug.cgi?id=90817 --- Comment #1 from Tom Hughes --- Created attachment 116240 --> https://bugs.freedesktop.org/attachment.cgi?id=116240&action=edit Output of glxinfo run locally on the X server -- You are receiving this mail because: You are the QA Contact fo

[Mesa-dev] [Bug 90817] swrast fails to load with certain remote X servers

https://bugs.freedesktop.org/show_bug.cgi?id=90817 Bug ID: 90817 Summary: swrast fails to load with certain remote X servers Product: Mesa Version: 10.5 Hardware: Other OS: All Status: NEW Severity: normal

Re: [Mesa-dev] [PATCH resend 7/7] i965: Disable HW-binding tables on batch finish for Broadwell

On 06/02/2015 09:31 AM, Kenneth Graunke wrote: > On Monday, June 01, 2015 03:14:30 PM Abdiel Janulgue wrote: >> This is needed since kernel doesn't support RS context save and >> restore on BDW yet. So manually disable hw-generated binding tables >> when done using it in the batch. Otherwise the

Re: [Mesa-dev] [PATCH resend 5/7] i965: Upload binding tables in hw-generated binding table format.

On 06/02/2015 11:25 AM, Kenneth Graunke wrote: > On Tuesday, June 02, 2015 12:58:29 AM Kenneth Graunke wrote: >> As I mentioned in my reply to patch 3, I think you need some sort of >> "did the buffer fill up?" check. Perhaps make a function to reserve >> space, advancing next_offset and returni

Re: [Mesa-dev] [PATCH] mesa: fix program resource queries for builtin variables

On 02/06/15 13:30, Tapani Pälli wrote: Patch fixes special cases with gl_VertexID and sets all builtin variables locations as '-1' as specified by the extension spec. Fixes ES 3.1 conformance test failure: ES31-CTS.program_interface_query.input-built-in Signed-off-by: Tapani Pälli ---

Re: [Mesa-dev] [PATCH resend 1/7] i965: Define HW-binding table and resource streamer control opcodes

On 06/02/2015 11:05 AM, Kenneth Graunke wrote: > On Monday, June 01, 2015 03:14:24 PM Abdiel Janulgue wrote: >> v2: Simplify HW binding table bit definitions and magic constants (Topi) >> v3: Add Broadwell support. >> >> Cc: kristian.h.kristen...@intel.com >> Cc: topi.pohjolai...@intel.com >> Cc:

Re: [Mesa-dev] [PATCH] nir: prevent use-after-free condition in should_lower_phi()

On 06/02/2015 01:42 PM, Eduardo Lima Mitev wrote: > lower_phis_to_scalar() pass recurses the instruction dependence graph to > determine if all the sources of a given instruction are scalarizable. > To prevent cycles, it temporary marks the phi instruction before recursing in, > then updates the en

[Mesa-dev] [PATCH] nir: prevent use-after-free condition in should_lower_phi()

lower_phis_to_scalar() pass recurses the instruction dependence graph to determine if all the sources of a given instruction are scalarizable. To prevent cycles, it temporary marks the phi instruction before recursing in, then updates the entry with the resulting value. However, it does not conside

Re: [Mesa-dev] [PATCH 2/2] nir: use src for ssa helper

Both of these look good and are: Reviewed-by: Thomas Helland 2015-06-02 11:37 GMT+02:00 Timothy Arceri : > --- > src/glsl/nir/glsl_to_nir.cpp | 5 + > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp > index af758ce.

Re: [Mesa-dev] [RFC v2 12/15] i965: correct VALIGN for 2d textures on Skylake

Actually, having said that I think it would make more sense to change the line to: return brw->gen >= 9 ? j * 4 : j; The 4 that it was returning for Gen<9 is supposed to represent the block height and I don't think there's any reason to hard-code it seeing as we are now querying the block h

[Mesa-dev] [PATCH] mesa: fix program resource queries for builtin variables

Patch fixes special cases with gl_VertexID and sets all builtin variables locations as '-1' as specified by the extension spec. Fixes ES 3.1 conformance test failure: ES31-CTS.program_interface_query.input-built-in Signed-off-by: Tapani Pälli --- src/mesa/main/shader_query.cpp | 22

[Mesa-dev] [PATCH 2/2] nir: use src for ssa helper

--- src/glsl/nir/glsl_to_nir.cpp | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp index af758ce..a471a86 100644 --- a/src/glsl/nir/glsl_to_nir.cpp +++ b/src/glsl/nir/glsl_to_nir.cpp @@ -932,11 +932,8 @@ nir_visitor:

[Mesa-dev] [PATCH 1/2] nir: remove extra semicolon

--- src/glsl/nir/nir_lower_atomics.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/glsl/nir/nir_lower_atomics.c b/src/glsl/nir/nir_lower_atomics.c index f6f8902..0457de6 100644 --- a/src/glsl/nir/nir_lower_atomics.c +++ b/src/glsl/nir/nir_lower_atomics.c @@ -109,7 +109,7

Re: [Mesa-dev] [PATCH resend 5/7] i965: Upload binding tables in hw-generated binding table format.

On Tuesday, June 02, 2015 12:58:29 AM Kenneth Graunke wrote: > As I mentioned in my reply to patch 3, I think you need some sort of > "did the buffer fill up?" check. Perhaps make a function to reserve > space, advancing next_offset and returning the offset to use: > > static uint32_t > reserve_h

Re: [Mesa-dev] [PATCH resend 1/7] i965: Define HW-binding table and resource streamer control opcodes

On Monday, June 01, 2015 03:14:24 PM Abdiel Janulgue wrote: > v2: Simplify HW binding table bit definitions and magic constants (Topi) > v3: Add Broadwell support. > > Cc: kristian.h.kristen...@intel.com > Cc: topi.pohjolai...@intel.com > Cc: kenn...@whitecape.org > Reviewed-by: Topi Pohjolainen

Re: [Mesa-dev] [PATCH resend 5/7] i965: Upload binding tables in hw-generated binding table format.

On Monday, June 01, 2015 03:14:28 PM Abdiel Janulgue wrote: > When hardware-generated binding tables are enabled, use the hw-generated > binding table format when uploading binding table state. > > Normally, the CS will will just consume the binding table pointer commands > as pipelined state. Whe

Re: [Mesa-dev] [PATCH resend 3/7] i965: Enable hardware-generated binding tables on render path.

On Monday, June 01, 2015 03:14:26 PM Abdiel Janulgue wrote: > This patch implements the binding table enable command which is also > used to allocate a binding table pool where where hardware-generated > binding table entries are flushed into. Each binding table offset in > the binding table pool i