On Tue, Jun 02, 2015 at 11:09:31AM -0700, Anuj Phogat wrote:
> and change the name to brw_miptree_choose_tiling().
>
> V3: Remove redundant function parameters. (Topi)
>
> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
> Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
> ---
> Comment made by Topi on patch 02/22 is fixed in V3 of this patch.
Thanks Anuj, looks good to me, and you already have my tag.
>
> src/mesa/drivers/dri/i965/brw_tex_layout.c | 107
> +++++++++++++++++++++++++-
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 104 -------------------------
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 8 --
> 3 files changed, 103 insertions(+), 116 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> index 4e79cf5..c77c0ce 100644
> --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> @@ -458,6 +458,108 @@ brw_miptree_layout_texture_3d(struct brw_context *brw,
> align_cube(mt);
> }
>
> +/**
> + * \brief Helper function for intel_miptree_create().
> + */
> +static uint32_t
> +brw_miptree_choose_tiling(struct brw_context *brw,
> + enum intel_miptree_tiling_mode requested,
> + const struct intel_mipmap_tree *mt)
> +{
> + if (mt->format == MESA_FORMAT_S_UINT8) {
> + /* The stencil buffer is W tiled. However, we request from the kernel a
> + * non-tiled buffer because the GTT is incapable of W fencing.
> + */
> + return I915_TILING_NONE;
> + }
> +
> + /* Some usages may want only one type of tiling, like depth miptrees (Y
> + * tiled), or temporary BOs for uploading data once (linear).
> + */
> + switch (requested) {
> + case INTEL_MIPTREE_TILING_ANY:
> + break;
> + case INTEL_MIPTREE_TILING_Y:
> + return I915_TILING_Y;
> + case INTEL_MIPTREE_TILING_NONE:
> + return I915_TILING_NONE;
> + }
> +
> + if (mt->num_samples > 1) {
> + /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
> + * Surface"):
> + *
> + * [DevSNB+]: For multi-sample render targets, this field must be
> + * 1. MSRTs can only be tiled.
> + *
> + * Our usual reason for preferring X tiling (fast blits using the
> + * blitting engine) doesn't apply to MSAA, since we'll generally be
> + * downsampling or upsampling when blitting between the MSAA buffer
> + * and another buffer, and the blitting engine doesn't support that.
> + * So use Y tiling, since it makes better use of the cache.
> + */
> + return I915_TILING_Y;
> + }
> +
> + GLenum base_format = _mesa_get_format_base_format(mt->format);
> + if (base_format == GL_DEPTH_COMPONENT ||
> + base_format == GL_DEPTH_STENCIL_EXT)
> + return I915_TILING_Y;
> +
> + /* 1D textures (and 1D array textures) don't get any benefit from tiling,
> + * in fact it leads to a less efficient use of memory space and bandwidth
> + * due to tile alignment.
> + */
> + if (mt->logical_height0 == 1)
> + return I915_TILING_NONE;
> +
> + int minimum_pitch = mt->total_width * mt->cpp;
> +
> + /* If the width is much smaller than a tile, don't bother tiling. */
> + if (minimum_pitch < 64)
> + return I915_TILING_NONE;
> +
> + if (ALIGN(minimum_pitch, 512) >= 32768 ||
> + mt->total_width >= 32768 || mt->total_height >= 32768) {
> + perf_debug("%dx%d miptree too large to blit, falling back to untiled",
> + mt->total_width, mt->total_height);
> + return I915_TILING_NONE;
> + }
> +
> + /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
> + if (brw->gen < 6)
> + return I915_TILING_X;
> +
> + /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
> + * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either
> TileX
> + * or Linear."
> + * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
> + * all the way back to 965, but is permitted on Gen7+.
> + */
> + if (brw->gen < 7 && mt->cpp >= 16)
> + return I915_TILING_X;
> +
> + /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
> + * messages), on p64, under the heading "Surface Vertical Alignment":
> + *
> + * This field must be set to VALIGN_4 for all tiled Y Render Target
> + * surfaces.
> + *
> + * So if the surface is renderable and uses a vertical alignment of 2,
> + * force it to be X tiled. This is somewhat conservative (it's possible
> + * that the client won't ever render to this surface), but it's difficult
> + * to know that ahead of time. And besides, since we use a vertical
> + * alignment of 4 as often as we can, this shouldn't happen very often.
> + */
> + if (brw->gen == 7 && mt->align_h == 2 &&
> + brw->format_supported_as_render_target[mt->format]) {
> + return I915_TILING_X;
> + }
> +
> + return I915_TILING_Y | I915_TILING_X;
> +}
> +
> +
> void
> brw_miptree_layout(struct brw_context *brw,
> bool for_bo,
> @@ -562,9 +664,6 @@ brw_miptree_layout(struct brw_context *brw,
> }
>
> if (!for_bo)
> - mt->tiling = intel_miptree_choose_tiling(brw, mt->format,
> - mt->logical_width0,
> - mt->num_samples,
> - requested, mt);
> + mt->tiling = brw_miptree_choose_tiling(brw, requested, mt);
> }
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 8966f89..3610030 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -469,110 +469,6 @@ intel_miptree_create_layout(struct brw_context *brw,
> return mt;
> }
>
> -/**
> - * \brief Helper function for intel_miptree_create().
> - */
> -uint32_t
> -intel_miptree_choose_tiling(struct brw_context *brw,
> - mesa_format format,
> - uint32_t width0,
> - uint32_t num_samples,
> - enum intel_miptree_tiling_mode requested,
> - struct intel_mipmap_tree *mt)
> -{
> - if (format == MESA_FORMAT_S_UINT8) {
> - /* The stencil buffer is W tiled. However, we request from the kernel a
> - * non-tiled buffer because the GTT is incapable of W fencing.
> - */
> - return I915_TILING_NONE;
> - }
> -
> - /* Some usages may want only one type of tiling, like depth miptrees (Y
> - * tiled), or temporary BOs for uploading data once (linear).
> - */
> - switch (requested) {
> - case INTEL_MIPTREE_TILING_ANY:
> - break;
> - case INTEL_MIPTREE_TILING_Y:
> - return I915_TILING_Y;
> - case INTEL_MIPTREE_TILING_NONE:
> - return I915_TILING_NONE;
> - }
> -
> - if (num_samples > 1) {
> - /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
> - * Surface"):
> - *
> - * [DevSNB+]: For multi-sample render targets, this field must be
> - * 1. MSRTs can only be tiled.
> - *
> - * Our usual reason for preferring X tiling (fast blits using the
> - * blitting engine) doesn't apply to MSAA, since we'll generally be
> - * downsampling or upsampling when blitting between the MSAA buffer
> - * and another buffer, and the blitting engine doesn't support that.
> - * So use Y tiling, since it makes better use of the cache.
> - */
> - return I915_TILING_Y;
> - }
> -
> - GLenum base_format = _mesa_get_format_base_format(format);
> - if (base_format == GL_DEPTH_COMPONENT ||
> - base_format == GL_DEPTH_STENCIL_EXT)
> - return I915_TILING_Y;
> -
> - /* 1D textures (and 1D array textures) don't get any benefit from tiling,
> - * in fact it leads to a less efficient use of memory space and bandwidth
> - * due to tile alignment.
> - */
> - if (mt->logical_height0 == 1)
> - return I915_TILING_NONE;
> -
> - int minimum_pitch = mt->total_width * mt->cpp;
> -
> - /* If the width is much smaller than a tile, don't bother tiling. */
> - if (minimum_pitch < 64)
> - return I915_TILING_NONE;
> -
> - if (ALIGN(minimum_pitch, 512) >= 32768 ||
> - mt->total_width >= 32768 || mt->total_height >= 32768) {
> - perf_debug("%dx%d miptree too large to blit, falling back to untiled",
> - mt->total_width, mt->total_height);
> - return I915_TILING_NONE;
> - }
> -
> - /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
> - if (brw->gen < 6)
> - return I915_TILING_X;
> -
> - /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
> - * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either
> TileX
> - * or Linear."
> - * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
> - * all the way back to 965, but is permitted on Gen7+.
> - */
> - if (brw->gen < 7 && mt->cpp >= 16)
> - return I915_TILING_X;
> -
> - /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
> - * messages), on p64, under the heading "Surface Vertical Alignment":
> - *
> - * This field must be set to VALIGN_4 for all tiled Y Render Target
> - * surfaces.
> - *
> - * So if the surface is renderable and uses a vertical alignment of 2,
> - * force it to be X tiled. This is somewhat conservative (it's possible
> - * that the client won't ever render to this surface), but it's difficult
> - * to know that ahead of time. And besides, since we use a vertical
> - * alignment of 4 as often as we can, this shouldn't happen very often.
> - */
> - if (brw->gen == 7 && mt->align_h == 2 &&
> - brw->format_supported_as_render_target[format]) {
> - return I915_TILING_X;
> - }
> -
> - return I915_TILING_Y | I915_TILING_X;
> -}
> -
>
> /**
> * Choose an appropriate uncompressed format for a requested
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> index 1d51546..0db6b44 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> @@ -784,14 +784,6 @@ intel_miptree_unmap(struct brw_context *brw,
> unsigned int level,
> unsigned int slice);
>
> -uint32_t
> -intel_miptree_choose_tiling(struct brw_context *brw,
> - mesa_format format,
> - uint32_t width0,
> - uint32_t num_samples,
> - enum intel_miptree_tiling_mode requested,
> - struct intel_mipmap_tree *mt);
> -
> void
> intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
> unsigned int level, unsigned int layer, enum gen6_hiz_op op);
> --
> 1.9.3
>
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