This will be used to implement the Gateway Barrier SEND needed to implement
the barrier function.
v2:
* notify => gateway_notify (Ken)
* combine short lines of brw_barrier proto/decl (mattst88)
Signed-off-by: Jordan Justen
Reviewed-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_eu.h
This will be used by the wait instruction when implementing the barrier()
function.
v2:
* Changes suggested by mattst88
Signed-off-by: Jordan Justen
Reviewed-by: Chris Forbes
Reviewed-by: Matt Turner
---
src/mesa/drivers/dri/i965/brw_reg.h | 16
1 file changed, 16 insertions
Signed-off-by: Jordan Justen
Reviewed-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_defines.h| 5 +
src/mesa/drivers/dri/i965/brw_fs.h | 3 +++
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 11 +++
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 27
Signed-off-by: Jordan Justen
Reviewed-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 63b1c79..bcddff7 100644
--- a/src/mesa/drivers/dr
git://people.freedesktop.org/~jljusten/mesa i965-barrier-v2
This series had a fair amount of comments & r-b from v1. Patches 9 &
10 probably would be the most import to look at.
Chris Forbes (2):
glsl: Add ir node for barrier
glsl: Add builtin barrier() function
Jordan Justen (9):
nir: Add
Signed-off-by: Jordan Justen
Reviewed-by: Chris Forbes
Reviewed-by: Connor Abbott
Reviewed-by: Ben Widawsky
---
src/glsl/nir/glsl_to_nir.cpp | 4 +++-
src/glsl/nir/nir_intrinsics.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir
This will be used to implement the barrier function.
v2:
* Rename to brw_WAIT (mattst88)
Signed-off-by: Jordan Justen
Reviewed-by: Chris Forbes
Reviewed-by: Matt Turner
---
src/mesa/drivers/dri/i965/brw_eu.h | 2 ++
src/mesa/drivers/dri/i965/brw_eu_emit.c | 21 +
2
From: Chris Forbes
v2:
* Changes suggested by mattst88
[jordan.l.jus...@intel.com: Add nir support]
Signed-off-by: Jordan Justen
Reviewed-by: Ben Widawsky
---
src/glsl/ir.h | 24
src/glsl/ir_hierarchical_visitor.cpp | 9 +++
These fields will be used when emitting a send for the barrier function.
Reference: IVB PRM Volume 4, Part 2, Section 1.1.1 Message Descriptor
v2:
* notify => gateway_notify (Ken)
* define bits for gen4-gen6 (bwidawsk, Ken)
Signed-off-by: Jordan Justen
Reviewed-by: Chris Forbes
Reviewed-by:
From: Chris Forbes
[jordan.l.jus...@intel.com: Add CS support]
Signed-off-by: Jordan Justen
Reviewed-by: Ben Widawsky
---
src/glsl/builtin_functions.cpp | 29 +
1 file changed, 29 insertions(+)
diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_function
Signed-off-by: Jordan Justen
Reviewed-by: Chris Forbes
Reviewed-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_defines.h | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 35c71d6..719db68 1006
Signed-off-by: Jordan Justen
Reviewed-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_disasm.c | 16
1 file changed, 16 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
b/src/mesa/drivers/dri/i965/brw_disasm.c
index 95e262a..bbca08c 100644
--- a/src/mesa/dr
On 2015-03-22 19:57:47, Chris Forbes wrote:
> Jordan,
>
> You also need to set m0.2:15 (Barrier count enable) and m0.2:14-9
> (Barrier count) to have the message gateway actually collect the
> proper number of threads, right?
Looking at IVB PRM, Vol 4, Part 2, 1.1.5.2 Message Payload
Under M0.2,
On Sat, Apr 25, 2015 at 05:39:20PM -0700, Jordan Justen wrote:
> On 2015-04-25 13:54:41, Ben Widawsky wrote:
> > On Fri, Apr 24, 2015 at 04:33:06PM -0700, Jordan Justen wrote:
> > > Add some values for gen7 & gen8. These are the number threads in a
> > > subslice.
> >
> > I forget if I asked this
On 2015-04-25 13:54:41, Ben Widawsky wrote:
> On Fri, Apr 24, 2015 at 04:33:06PM -0700, Jordan Justen wrote:
> > Add some values for gen7 & gen8. These are the number threads in a
> > subslice.
>
> I forget if I asked this in the v1, but shouldn't we be moving to the
> awful^wrequired kernel inter
On Sat, Apr 25, 2015 at 6:57 PM, Bruno Jimenez wrote:
> On Sat, 2015-04-25 at 15:00 -0400, Ilia Mirkin wrote:
>> Signed-off-by: Ilia Mirkin
>> ---
>> docs/relnotes/10.6.0.html | 7 ---
>> src/gallium/drivers/freedreno/a3xx/fd3_rasterizer.c | 2 ++
>> src/gallium/dri
On Sat, 2015-04-25 at 15:00 -0400, Ilia Mirkin wrote:
> Signed-off-by: Ilia Mirkin
> ---
> docs/relnotes/10.6.0.html | 7 ---
> src/gallium/drivers/freedreno/a3xx/fd3_rasterizer.c | 2 ++
> src/gallium/drivers/freedreno/freedreno_screen.c| 2 +-
> 3 files changed
On Sat, 2015-04-25 at 18:46 +0200, Alejandro Piñeiro wrote:
> There was a typo on commit c0cd5b, doing it when explicit_binding
> was false. This prevented to use any binding point different to 0.
> ---
>
> Taking into account the explanation on the header about the
> variable binding (ast.h:553)
On Fri, Apr 24, 2015 at 04:33:06PM -0700, Jordan Justen wrote:
> Add some values for gen7 & gen8. These are the number threads in a
> subslice.
I forget if I asked this in the v1, but shouldn't we be moving to the
awful^wrequired kernel interface which exposes this information? I think for BSW
it'
On Fri, Apr 24, 2015 at 4:11 PM, Axel Davy wrote:
> +if (damaged) {
> +box = *damaged;
> +box.z = This->layer;
> +box.depth = 1;
> +} else {
> +box.x = 0;
> +box.y = 0;
> +box.z = This->layer;
> +box.width = This->desc.Width;
> +
As per IRC discussion, ignore -- I thought a user could hit this, but
the pool is checked in CopySurface's callers.
On Sat, Apr 25, 2015 at 4:23 PM, Ilia Mirkin wrote:
> On Fri, Apr 24, 2015 at 4:11 PM, Axel Davy wrote:
>> Copying to/from a Managed texture is forbidden.
>> Rendering to a Managed
On Fri, Apr 24, 2015 at 4:11 PM, Axel Davy wrote:
> Copying to/from a Managed texture is forbidden.
> Rendering to a Managed texture is forbidden.
>
> Signed-off-by: Axel Davy
> ---
> src/gallium/state_trackers/nine/surface9.c | 23 +--
> src/gallium/state_trackers/nine/volum
From: Roland Scheidegger
Hopefully this is the last one now (for texture X32_S8X24_UINT views).
+4 piglits.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90167
---
src/gallium/auxiliary/util/u_tile.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/au
When there is a colormask active that does not cover all of the format,
enabling reading in the destination like with a combining blend
operation. This fixes fbo-blending-formats on a3xx.
Signed-off-by: Ilia Mirkin
---
Experimentally, RGB10_A2 does not need this... weird, but wtvr.
src/gallium
On Saturday, April 25, 2015 12:14:38 PM Jordan Justen wrote:
> On 2015-04-24 23:38:15, Kenneth Graunke wrote:
> > On Friday, April 24, 2015 04:33:11 PM Jordan Justen wrote:
> > > + int dw = 0;
> > > + desc[dw++] = brw->cs.base.prog_offset;
> > > + if (brw->gen >= 8)
> > > + dw++; /* Kern
On 2015-04-24 23:38:15, Kenneth Graunke wrote:
> On Friday, April 24, 2015 04:33:11 PM Jordan Justen wrote:
> > + int dw = 0;
> > + desc[dw++] = brw->cs.base.prog_offset;
> > + if (brw->gen >= 8)
> > + dw++; /* Kernel Start Pointer High */
> > + dw++;
> > + dw++;
> > + desc[dw++] =
Enables ARB_depth_buffer_float. There is no sampling support for
interleaved Z32F_S8, so we store the two textures separately, one as
Z32F, the other as S8. As a result, we need a lot of additional logic
for restores and transfers.
Signed-off-by: Ilia Mirkin
---
docs/relnotes/10.6.0.html
32-bit depth buffers are stored as unorm, and thus need special handling
when moving to and from gmem. They are copied into gmem by writing
depth, and resolved from gmem using a special resolve bit which
apparently float-ifies the data.
Signed-off-by: Ilia Mirkin
---
src/gallium/drivers/freedren
Signed-off-by: Ilia Mirkin
---
docs/relnotes/10.6.0.html | 7 ---
src/gallium/drivers/freedreno/a3xx/fd3_rasterizer.c | 2 ++
src/gallium/drivers/freedreno/freedreno_screen.c| 2 +-
3 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/docs/relnotes/10.6
Signed-off-by: Ilia Mirkin
---
src/gallium/drivers/freedreno/freedreno_context.c | 2 +-
src/gallium/drivers/freedreno/freedreno_resource.c | 4 +++-
src/gallium/drivers/freedreno/freedreno_resource.h | 11 +++
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/src/gallium
On 2015-04-24 23:42:58, Kenneth Graunke wrote:
> On Friday, April 24, 2015 04:33:03 PM Jordan Justen wrote:
> > From: Paul Berry
> >
> > jordan.l.jus...@intel.com:
> > * Added brw_cs_prog_key structure
> > * Added brw_cs_prog_data::dispatch_grf_start_reg_16
> > * Added brw_cs_prog_data::no_8
>
Reviewed-by: Matt Turner
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Code generation is not allowed to fail for any reason - in fact,
fs_generator has no mechanism for failing. The visitor is responsible
for that.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/me
There was a typo on commit c0cd5b, doing it when explicit_binding
was false. This prevented to use any binding point different to 0.
---
Taking into account the explanation on the header about the
variable binding (ast.h:553)
/**
* Binding specified via GL_ARB_shading_language_420pack's "b
Am 25.04.2015 um 09:58 schrieb Axel Davy:
> Le 24/04/2015 23:42, Henri Verbeet a écrit :
>> On 24 April 2015 at 22:09, Axel Davy wrote:
>>> +static void nine_setup_fpu(void)
>>> +{
>>> +#if defined(__GNUC__) && (defined(__i386__) || defined(__x86_64__))
>>> +WORD cw;
>>> +__asm__ volatile
On 25 April 2015 at 09:18, Ilia Mirkin wrote:
> Now that ARB_texture_stencil8 is supported, this might happen.
Seems logical, would be nice to have a piglit for it,
Reviewed-by: Dave Airlie
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http
https://bugs.freedesktop.org/show_bug.cgi?id=89599
--- Comment #4 from Tomasz Paweł Gajc ---
Created attachment 115318
--> https://bugs.freedesktop.org/attachment.cgi?id=115318&action=edit
Potential fix
--
You are receiving this mail because:
You are the QA Contact for the bug.
You are the as
Le 25/04/2015 10:15, Henri Verbeet a écrit :
The comment is misleading, because the code does more than that.
(Hint: What happens to rounding and precision control?)
But really, please either explicitly tell people they can't look at
Wine (D3D related) source if they want to contribute to st/ni
On 25 April 2015 at 09:58, Axel Davy wrote:
> static void nine_setup()
> {
> fpu_control_t c;
>
> _FPU_GETCW(c);
> /* clear the control word */
> c &= _FPU_RESERVED;
> /* enable interrupts (d3d9 doc, wine tests) */
> c |= _FPU_MASK_IM | _FPU_MASK_DM | _FPU_MASK_ZM | _FPU_MA
Le 24/04/2015 23:42, Henri Verbeet a écrit :
On 24 April 2015 at 22:09, Axel Davy wrote:
+static void nine_setup_fpu(void)
+{
+#if defined(__GNUC__) && (defined(__i386__) || defined(__x86_64__))
+WORD cw;
+__asm__ volatile ("fnstcw %0" : "=m" (cw));
+cw = (cw & ~0xf3f) | 0x3f;
+
40 matches
Mail list logo
