Re: [Mesa-dev] [PATCH 3/3] mesa: add missing error checks in _mesa_GetObject[Ptr]Label()

Hi Brian, Maybe its just another oversight in the spec but I thought I'd point out that the spec doesnt actually say to test for this in the get label functions. I assumed this was because label can be NULL in which case a bufSize of 0 would be valid. I haven't checked what the Catalyst drivers

Re: [Mesa-dev] [PATCH 15/15] i965/gen6+: Support 128 varying components.

On 09/03/2013 04:18 PM, Paul Berry wrote: > GL 3.2 requires us to support 128 varying components for geometry > shader outputs and fragment shader inputs, and 64 varying components > otherwise. But there's no hardware limitation that restricts us to 64 > varying components, and core Mesa doesn't c

Re: [Mesa-dev] [PATCH 11/15] i965/fs: When >64 input components, order them to match prev pipeline stage.

On 09/03/2013 04:18 PM, Paul Berry wrote: > Since the SF/SBE stage is only capable of performing arbitrary > reorderings of 16 varying slots, we can't arrange the fragment shader > inputs in an arbitrary order if there are more than 16 input varying > slots in use. We need to make sure that slots

Re: [Mesa-dev] [PATCH 05/15] i965/sf: Consolidate common code for setting up gen6-7 attribute overrides.

On 09/03/2013 04:18 PM, Paul Berry wrote: > --- > src/mesa/drivers/dri/i965/brw_state.h | 9 +- > src/mesa/drivers/dri/i965/gen6_sf_state.c | 153 > +- > src/mesa/drivers/dri/i965/gen7_sf_state.c | 64 + > 3 files changed, 97 insertions(+), 129 delet

Re: [Mesa-dev] [PATCH] i965/hsw: compute DDX in a subspan based only on top row

On Fri, Sep 13, 2013 at 2:15 PM, Paul Berry wrote: > On 12 September 2013 22:06, Chia-I Wu wrote: > >> From: Chia-I Wu >> >> Consider only the top-left and top-right pixels to approximate DDX in a >> 2x2 >> subspan, unless the application or the user requests a more accurate >> approximation.

[Mesa-dev] [PATCH] xdemos/corender: remove obsolete function gethostbyname

From 911cdbcf90440d748c185ac53fa6dded7f3da17c Mon Sep 17 00:00:00 2001 From: David Heidelberger Date: Mon, 9 Sep 2013 21:48:36 +0200 Subject: [PATCH] xdemos/corender: remove obsolete function gethostbyname Patch remove unused and obsolete funtion gethostbyname(). This also fixes runtime assert a

Re: [Mesa-dev] gallium-bind-sampler-states branch

On Sun, Sep 15, 2013 at 12:24 AM, Brian Paul wrote: > On 09/12/2013 09:06 PM, Chia-I Wu wrote: >> >> Hi Brian, >> >> On Fri, Sep 13, 2013 at 8:46 AM, Brian Paul wrote: >>> >>> >>> I just pushed a gallium-bind-sampler-states branch to my git repo at >>> git://people.freedesktop.org/~brianp/mesa >>

Re: [Mesa-dev] [PATCH] vdpau/decode: Check max width and max height.

Reviewed and committed. Thanks, Christian. - Ursprüngliche Mail - Von: "Rico Schüller" An: mesa-dev@lists.freedesktop.org CC: "Rico Schüller" Gesendet: Samstag, 14. September 2013 20:27:07 Betreff: [Mesa-dev] [PATCH] vdpau/decode: Check max width and max height. --- src/galli

[Mesa-dev] [PATCH] i965: Fix cube array coordinate normalization

Hardware requires the magnitude of the largest component to not exceed 1; brw_cubemap_normalize ensures that this is the case. Unfortunately, we would previously multiply the array index for cube arrays by the normalization factor. The incorrect array index would then cause the sampler to attempt

[Mesa-dev] [PATCH V3 11/11] i965: Enable ARB_texture_gather on Gen7

Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_context.c | 1 + src/mesa/drivers/dri/i965/intel_extensions.c | 4 2 files changed, 5 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 4fcc9fb..96d1ff4 10064

[Mesa-dev] [PATCH V3 10/11] i965: use gather slots in the binding table for gather4.

Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 8 ++-- src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | 8 ++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp b/src/mesa/drivers/dri/i965/brw_fs_emit.cp

[Mesa-dev] [PATCH V3 09/11] i965: Emit a second set of SURFACE_STATE for gather4 from textures.

This allows us to use a different surface format for gather4, which is required for R32G32_FLOAT to work on Gen7. Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_context.h | 3 +- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 57 ++- src/mesa/dr

[Mesa-dev] [PATCH V3 08/11] i965: make room in the binding table for a full alternate set of surface_states

Worst-case is that *every* texunit uses a format that needs overriding. Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_context.h | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_conte

[Mesa-dev] [PATCH V3 07/11] i965: Add BRW_SURFACEFORMAT_R32G32_FLOAT_LD, required for IVB gather4 w/a

gather4 GREEN channel against a surface with format R32G32_FLOAT doesn't work correctly on IVB. w/a from bspec: - use R32G32_FLOAT_LD = 0x97 instead, for gather4 only. - select BLUE channel to read GREEN Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_defines.h | 1 +

[Mesa-dev] [PATCH V3 06/11] i965: w/a for gather4 green RG32F

Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4 src/mesa/drivers/dri/i965/brw_program.h| 5 + src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 4 src/mesa/drivers/dri/i965/brw_wm.c | 9 + 4 files changed, 22 insertions(

[Mesa-dev] [PATCH V3 05/11] i965/vs: Add support for ir_tg4

Pretty much the same as the FS case. Channel select goes in the header, V2: Less mangling. V3: Avoid sampling at all, for degenerate swizzles. Signed-off-by: Chris Forbes --- src/mesa/drivers/dri/i965/brw_vec4.h | 1 + src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 46 +

[Mesa-dev] [PATCH V3 04/11] i965/fs: Add support for ir_tg4

Lowers ir_tg4 (from textureGather and textureGatherOffset builtins) to SHADER_OPCODE_TG4. The usual post-sampling swizzle workaround can't work for ir_tg4, so avoid doing that: * For R/G/B/A swizzles use the hardware channel select (lives in the same dword in the header as the texel offset), a

[Mesa-dev] [PATCH V3 03/11] i965: add SHADER_OPCODE_TG4

Adds the Gen7 message IDs, a new SHADER_OPCODE_TG4 pseudo-op, and low-level support for emitting it via generate_tex(). V3: Updated for changes in master. Signed-off-by: Chris Forbes Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_defines.h | 3 +++ src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH V3 02/11] glsl: add texture gather changes

From: Maxence Le Dore V2 [Chris Forbes]: - Add new pattern, fixup parameter reading. V3: Rebase onto new builtins machinery Reviewed-by: Kenneth Graunke --- src/glsl/builtin_functions.cpp | 35 +++ src/glsl/glcpp/glcpp-parse.y| 3 +++ src/glsl/

[Mesa-dev] [PATCH V3 01/11] mesa: add texture gather changes

From: Maxence Le Dore Reviewed-by: Kenneth Graunke --- src/mapi/glapi/gen/ARB_texture_gather.xml | 14 ++ src/mapi/glapi/gen/gl_API.xml | 2 +- src/mesa/main/context.c | 4 src/mesa/main/extensions.c| 1 + src/mesa/main/get.c

[Mesa-dev] [PATCH V3 00/11] ARB_texture_gather for i965 Gen7

This series adds support for ARB_texture_gather. Patches 1-2 add the core mesa and GLSL compiler scaffolding for the extension; Patches 3-5 add basic support to the i965 driver; Patches 6-10 work around a hardware bug which causes incorrect sampling of R32G32_FLOAT surfaces; Patch 11 turns everyt

[Mesa-dev] [PATCH 24/24] i965: Simplify the shader time code by using atomic counter helpers.

--- src/mesa/drivers/dri/i965/brw_eu_emit.c | 25 --- src/mesa/drivers/dri/i965/brw_state.h | 2 -- src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 4 +++- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 +++- src/mesa/drivers/dri/i965/gen7_wm

[Mesa-dev] [PATCH 23/24] i965/gen7: Expose ARB_shader_atomic_counters.

--- src/mesa/drivers/dri/i965/brw_context.c | 10 ++ src/mesa/drivers/dri/i965/intel_extensions.c | 3 +++ 2 files changed, 13 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 4fcc9fb..2060764 100644 --- a/src/mesa/d

[Mesa-dev] [PATCH 22/24] i965/gen7: Handle atomic instructions from the VEC4 back-end.

This can deal with all the 15 32-bit untyped atomic operations the hardware supports, but only INC and PREDEC are going to be exposed through the API for now. --- src/mesa/drivers/dri/i965/brw_vec4.h | 7 +++ src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 64 ++

[Mesa-dev] [PATCH 21/24] i965/gen7: Handle atomic instructions from the FS back-end.

This can deal with all the 15 32-bit untyped atomic operations the hardware supports, but only INC and PREDEC are going to be exposed through the API for now. --- src/mesa/drivers/dri/i965/brw_fs.h | 7 +++ src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 83

[Mesa-dev] [PATCH 20/24] i965: Add brw_reg constructors taking a dynamically determined vector width.

The MRF variant is going to be used extensively by the next two patches to assemble untyped atomic and surface read messages easily. --- src/mesa/drivers/dri/i965/brw_reg.h | 24 1 file changed, 24 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_reg.h b/src/mesa

[Mesa-dev] [PATCH 6/6] gbm: Add support for gbm bos and surfaces using GBM_FORMAT_ARGB2101010

We can now add GBM support for the 10 bit/channel formats which lets us create a gbm surface that we can use with KMS for display hardware that support the format. Signed-off-by: Kristian Høgsberg --- src/gbm/backends/dri/gbm_dri.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/gb

[Mesa-dev] [PATCH 5/6] dri: Add __DRIimage support for the ARGB2101010 format

We add support for the ARGB2101010 color format to the DRI image extension, which allows DRI loaders to create a __DRIimage with this color format. Signed-off-by: Kristian Høgsberg --- include/GL/internal/dri_interface.h | 2 ++ src/mesa/drivers/dri/i965/intel_screen.c | 10 ++ 2 f

[Mesa-dev] [PATCH 4/6] i965: Create ARGB2101010 DRI configs

This commit enables ARGB2101010 system framebuffers (that is, DRI drawables) for the i965 drivers. This is done by generating DRI configs that advertise this color format as well as teaching intelCreateBuffer to pick the right color format when it sees such a DRI config. Signed-off-by: Kristian H

[Mesa-dev] [PATCH 3/6] dri/common: Add support for creating ARGB2101010 configs

This extends the common dri driver infrastructure with the ability to create __DRIconfigs for 10 bits/channel + 2 bit alphs formats. This still has to be supported and requested by a driver, so this doesn't enable anthing yet. Signed-off-by: Kristian Høgsberg --- src/mesa/drivers/dri/common/uti

[Mesa-dev] [PATCH 2/6] egl_dri2: Remove depth argument from dri2_add_config()

All callers now use the more correct rgba mask mechanism for filtering out mathcing DRI configs. Even if depth and buffer size match, the color component layout can be different, or in case or ARGB and ARGB2101010 the color components can even be different sizes. Since anything that the depth

[Mesa-dev] [PATCH 1/6] egl_dri2: Match X11 visuals using rgba masks instead of depth

Matching on visual depth to buffer size makes 8 bpc RGBA look similar to 10 bit RGB with 2 bit alphs - both have buffer size 32. Instead, build the rgba masks from the visual data and use that for finding matching DRI configs. We need to keep the special case that allows us to match 24 bit visual

[Mesa-dev] [PATCH 0/6] Support for 10 bpc EGLSurface

Hi, This little series adds support for creating EGLSurfaces with color buffers using the ARGB2101010 pixel format. We the new KMS addFB2 ioctl we can create KMS framebuffers with that format and this series ends up adding the pixel format to gbm so we can generate buffers with that format. The

[Mesa-dev] [PATCH 19/24] i965: Handle the 'atomic_uint' GLSL type.

--- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 ++ src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 1 + src/mesa/drivers/dri/i965/brw_shader.cpp | 1 + src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 4 +++- 4 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/mesa/dri

[Mesa-dev] [PATCH 17/24] i965/gen7: Implement code generation for untyped surface read instructions.

--- src/mesa/drivers/dri/i965/brw_defines.h | 1 + src/mesa/drivers/dri/i965/brw_eu.h | 8 + src/mesa/drivers/dri/i965/brw_eu_emit.c | 56 + src/mesa/drivers/dri/i965/brw_fs.cpp| 1 + src/mesa/drivers/dri/i965/brw_fs.h | 4 +++

[Mesa-dev] [PATCH 18/24] i965: Add a 'has_side_effects' back-end instruction predicate.

Analogous to the GLSL IR predicate with the same name. This patch fixes the three dead code elimination passes and the VEC4/FS instruction scheduling passes so they leave instructions with side effects alone. At some point it might be interesting to have the instruction scheduler calculate the ex

[Mesa-dev] [PATCH 15/24] i965: Implement ABO surface state emission.

The maximum number of atomic buffer objects is somewhat arbitrary, we can change it in the future easily if it turns out it's not enough... --- src/mesa/drivers/dri/i965/brw_context.h | 17 +++-- src/mesa/drivers/dri/i965/brw_gs_surface_state.c | 19 ++ src/mesa/drivers/dri/i9

[Mesa-dev] [PATCH 16/24] i965/gen7: Implement code generation for untyped atomic instructions.

--- src/mesa/drivers/dri/i965/brw_defines.h | 2 + src/mesa/drivers/dri/i965/brw_eu.h | 9 + src/mesa/drivers/dri/i965/brw_eu_emit.c | 62 + src/mesa/drivers/dri/i965/brw_fs.cpp| 2 + src/mesa/drivers/dri/i965/brw_fs.h | 5 +++

[Mesa-dev] [PATCH 13/24] glsl: Linker support for ARB_shader_atomic_counters.

--- src/glsl/Makefile.sources | 1 + src/glsl/link_atomics.cpp | 190 ++ src/glsl/linker.cpp | 15 src/glsl/linker.h | 7 ++ 4 files changed, 213 insertions(+) create mode 100644 src/glsl/link_atomics.cpp diff --git a/src/glsl/M

[Mesa-dev] [PATCH 14/24] i965: Define vtbl method that initializes an untyped R/W surface.

And add Gen7 implementation. --- src/mesa/drivers/dri/i965/brw_context.h | 7 + src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 35 +++ 2 files changed, 37 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers

[Mesa-dev] [PATCH 06/24] mesa: Add support for ARB_shader_atomic_counters.

This patch implements the common support code required for the ARB_shader_atomic_counters extension. It defines the necessary data structures for tracking atomic counter buffer objects (from now on "ABOs") associated with some specific context or shader program, it implements support for binding b

[Mesa-dev] [PATCH 10/24] glsl: Implement parser support for atomic counters.

--- src/glsl/ast.h| 15 ++ src/glsl/ast_to_hir.cpp | 68 +-- src/glsl/ast_type.cpp | 13 +++-- src/glsl/glsl_lexer.ll| 2 +- src/glsl/glsl_parser.yy | 13 +++-- src/glsl/glsl_parser_extras.h | 10 +

[Mesa-dev] [PATCH 12/24] glsl: Add predicate to determine if an IR node has side effects.

And fix the dead code elimination pass so atomic writes aren't optimized out in cases where the return value isn't used by the program. --- src/glsl/ir.h | 16 src/glsl/opt_dead_code.cpp | 3 ++- 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/src/glsl

[Mesa-dev] [PATCH 11/24] glsl: Add built-in functions and constants required for ARB_shader_atomic_counters.

--- src/glsl/builtin_functions.cpp | 33 + src/glsl/builtin_variables.cpp | 15 +++ src/glsl/glcpp/glcpp-parse.y| 3 +++ src/glsl/glsl_parser_extras.cpp | 6 ++ src/glsl/glsl_parser_extras.h | 7 +++ 5 files changed, 64 insertions(+)

[Mesa-dev] [PATCH 09/24] glsl: Add IR node for atomic operations.

Add a subclass of ir_rvalue that represents an atomic operation on some ir_variable. Also define a new IR visitor method, and implement IR builder, printer and reader support for it. --- src/glsl/ir.cpp| 2 +- src/glsl/ir.h | 42 ++

[Mesa-dev] [PATCH 05/24] glapi: Add support for ARB_shader_atomic_counters.

Add XML file for the dispatch code generator, update the dispatch_sanity test and add stub definition for the new entry point. --- src/mapi/glapi/gen/ARB_shader_atomic_counters.xml | 47 +++ src/mapi/glapi/gen/Makefile.am| 1 + src/mapi/glapi/gen/gl_API.xml

[Mesa-dev] [PATCH 07/24] glsl: Add extension enables for ARB_shader_atomic_counters.

--- src/glsl/glsl_parser_extras.cpp | 1 + src/glsl/glsl_parser_extras.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp index 772933f..ff34864 100644 --- a/src/glsl/glsl_parser_extras.cpp +++ b/src/glsl/glsl_parser_extras.

[Mesa-dev] [PATCH 04/24] ralloc: Unify overloads of the new operator and guarantee object destruction.

This patch introduces a pair of helper functions providing a common implementation of the "new" and "delete" operators for all C++ classes that are allocated by ralloc via placement new. The 'ralloc_new' helper function takes care of setting up an ralloc destructor callback that will call the appr

[Mesa-dev] [PATCH 08/24] glsl: Add new atomic_uint built-in GLSL type.

--- src/glsl/ast_to_hir.cpp | 1 + src/glsl/builtin_type_macros.h | 2 ++ src/glsl/builtin_types.cpp | 6 ++ src/glsl/glsl_types.cpp | 2 ++ src/glsl/glsl_types.h| 14 ++ src/glsl/

[Mesa-dev] [PATCH 03/24] i965: Initialize all member variables of vec4_instruction on construction.

Ditto. Otherwise some of its member variables are going to have uninitialized contents in cases where its memory is not allocated using rzalloc(). --- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 15 +++ 1 file changed, 15 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_

[Mesa-dev] [PATCH 01/24] mesa: Fix misplaced includes of "main/uniforms.h".

Several C++ source files include "main/uniforms.h" from an extern "C" block, which is both unnecessary, because "uniforms.h" already checks for a C++ compiler and sets the right linkage, and incorrect, because the header file includes other C++ headers ("glsl_types.h" and "ir_uniform.h") that are s

[Mesa-dev] [PATCH 02/24] glsl: Initialize all member variables of _mesa_glsl_parse_state on construction.

The _mesa_glsl_parse_state object relies on the memory allocator zeroing out its contents before it's initialized, which seems rather risky. One of the following commits will homogenize implementations of the new operator in a way that would break this assumption leaving some of the member variabl

[Mesa-dev] [PATCH 00/24] Support for ARB_shader_atomic_counters.

This patch series implements support for the ARB_shader_atomic_counters extension, which is part of GL core since GL 4.2. It includes patches adding support for the new APIs and GLSL language features, and working back-end code for Intel Gen7 hardware -- Ivy Bridge should work with these patches a