On 07/08/2013 04:09 PM, Matt Turner wrote:
Fixes MESA_GL_VERSION_OVERRIDE=3.2 egl-create-context-verify-gl-flavor.
---
src/mesa/main/context.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index 5ad04cc..d687fb7 1006
https://bugs.freedesktop.org/show_bug.cgi?id=60016
Chí-Thanh Christopher Nguyễn changed:
What|Removed |Added
See Also||https://bugs.freedesktop.o
Acked-by: Chris Forbes
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Reviewed-by: Jordan Justen
On Mon, Jul 8, 2013 at 4:09 PM, Matt Turner wrote:
> Fixes MESA_GL_VERSION_OVERRIDE=3.2 egl-create-context-verify-gl-flavor.
> ---
> src/mesa/main/context.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/main/context.c b/src/me
Fixes MESA_GL_VERSION_OVERRIDE=3.2 egl-create-context-verify-gl-flavor.
---
src/mesa/main/context.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
index 5ad04cc..d687fb7 100644
--- a/src/mesa/main/context.c
+++ b/src/mesa
On Tue, Jul 2, 2013 at 10:02 PM, Ian Romanick wrote:
> 3. I'd like to make some adjustments to our process for picking patches back
> to the stable branch. The current process is okay, but it has some kinks.
> The two big (related) problems are people either under-mark things for the
> stable bra
On 8 July 2013 10:40, Paul Berry wrote:
> Previously, we had a separate function for setting up the built-in
> variables for each combination of shader stage and GLSL version
> (e.g. generate_110_vs_variables to generate the built-in variables for
> GLSL 1.10 vertex shaders). The functions calle
On 3 July 2013 21:49, Kenneth Graunke wrote:
> On 07/03/2013 10:50 AM, Paul Berry wrote:
>
>> driver->ProgramStringNotify is only called for ARB programs, fixed
>> function vertex programs, and ir_to_mesa (which isn't used by the i965
>> back-end). Therefore, even after geometry shaders are adde
On 08.07.2013 22:32, Marek Olšák wrote:
> Hi Emil,
>
> What issue does this patch fix? Is there a nonarchaic CPU architecture
> or a compiler where "int" doesn't have 32 bits?
Yes, on x86_128 an int will be 64 bit.
It says "(Un)pack pixel blocks to/from R32G32B32A32_UINT", and not
PIPE_FORMAT_RSI
On 08/07/13 21:32, Marek Olšák wrote:
> Hi Emil,
>
> What issue does this patch fix? Is there a nonarchaic CPU architecture
> or a compiler where "int" doesn't have 32 bits?
>
Hi Marek
To the best of my knowledge, there is no specific issue. It was brought
up as I was looking on a nouveau crash.
Hi Emil,
What issue does this patch fix? Is there a nonarchaic CPU architecture
or a compiler where "int" doesn't have 32 bits?
Marek
On Mon, Jul 8, 2013 at 8:56 PM, Emil Velikov wrote:
> Every function but the above four uses explicitly sized types for their
> src and dst arguments. Even fetch
On Tue, Jul 02, 2013 at 02:37:54PM -0700, Matt Turner wrote:
> On Tue, Jul 2, 2013 at 1:02 PM, Ian Romanick wrote:
> > 2. Instead of just posting md5sum for the release tarballs, I think we
> > should start GPG signing them. I'm not sure what sort of process we want to
> > establish for this. Sh
Every function but the above four uses explicitly sized types for their
src and dst arguments. Even fetch_rgba_{s,u}int follows the convention.
Signed-off-by: Emil Velikov
---
src/gallium/auxiliary/util/u_format.c | 8
src/gallium/auxiliary/util/u_format.h | 8
2 files changed,
---
src/glsl/ast.h | 12
1 file changed, 12 insertions(+)
diff --git a/src/glsl/ast.h b/src/glsl/ast.h
index 3bb33c5..87f9876 100644
--- a/src/glsl/ast.h
+++ b/src/glsl/ast.h
@@ -453,6 +453,18 @@ class ast_declarator_list;
class ast_struct_specifier : public ast_node {
public:
+
Reviewed-by: Marek Olšák
Marek
On Fri, Jul 5, 2013 at 8:55 PM, Christoph Bumiller
wrote:
> From: Christoph Bumiller
>
> ---
> src/gallium/drivers/r600/evergreen_state.c | 10 --
> src/gallium/drivers/r600/r600_state.c | 10 --
> 2 files changed, 16 insertions(+), 4 deleti
Previously, we had a separate function for setting up the built-in
variables for each combination of shader stage and GLSL version
(e.g. generate_110_vs_variables to generate the built-in variables for
GLSL 1.10 vertex shaders). The functions called each other in ad-hoc
ways, leading to unexpected
gl_TexCoord was deprecated in GLSL 1.30. In GLSL 1.40 it was marked
as ARB_compatibility-only, and in GLSL 1.50 and above it was marked as
only appearing in the compatibility profile. It has never appeared in
GLSL ES.
However, Mesa erroneously included it in all desktop versions of GLSL,
even ve
Previously, we set it equal to MaxVertexUniformComponents. It should
be MaxVertexUniformComponents / 4.
NOTE: This is a candidate for the stable branches.
Cc: mesa-sta...@lists.freedesktop.org
---
src/glsl/builtin_variables.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
While hunting down some geometry shader bugs last week, I became
concerned about the organization of src/glsl/builtin_variables.cpp,
which is responsible for setting up all the GLSL built-in variables
accessible by a shader, based on the shader type (VS or FS), GLSL
version, desktop/GLES flag, and
ping
Does anyone have any objections on this patch? Feel free to commit, it
looks ok
Cheers
Emil
On 22/06/13 16:43, Emil Velikov wrote:
> Change egl_g3d_wl_drm_common_query_buffer() to use boolean/int rather than
> EGLBoolean/EGLint, based on the interface in native_wayland_bufmgr.h,
>
> Resolve
Resolves the following gcc warning
opt_flip_matrices.cpp:84:32: warning: unused variable 'deref'
v2: keep the variable, but wrap it in a ifndef NDEBUG block(suggested by Ian)
Signed-off-by: Emil Velikov
Reviewed-by: Kenneth Graunke
---
Feel free to commit
---
src/glsl/opt_flip_matrices.cpp |
Resolves the following gcc warnings
warning: 'iface_type_name' may be used uninitialized in this function
warning: 'var_mode' may be used uninitialized in this function
Note: The variables are initialised to UNKNOWN and ir_var_auto
Signed-off-by: Emil Velikov
Reviewed-by: Ian Romanick
---
Fe
Resolves the following gcc warning
warning: 'ptr' may be used uninitialized in this function
xy[0] = ptr[sample_index][0] * 0.0625f;
^
v2: Bail out when using non-conformant sample_count (spotted by calim)
Signed-off-by: Emil Velikov
---
src/gallium/drivers/nvc0/nvc0_contex
On Tue, Jul 02, 2013 at 10:44:10AM +0200, Niels Ole Salscheider wrote:
> Hi,
>
> the attached patches add initial support for double precision operations on
> Southern Islands cards.
>
> Some expressions containing multiple double precision kernel arguments cause
> llvm to run until all memory
On Tue, Jul 02, 2013 at 01:02:06PM -0700, Ian Romanick wrote:
> To keep our six-month release cadence, it looks like we'll target
> August 22nd for 9.2. That means we'll probably need to make the
> release branch on July 18th... that's just over two weeks from now.
>
> Assuming that works for eve
Address GPU hung due to skipping selection of 3D pipeline in blorp when RS
is switched on. I've yet to figure out the reason for this.
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/mesa/drivers/d
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 16 +++-
src/mesa/drivers/dri/i965/gen7_blorp.cpp |3 ++-
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blor
Update the hardware binding table when uploading a new UBO surface state
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c |5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/b
When the resource streamer encounters 3DSTATE_BINDING_TABLE_POINTERS_* command,
it will flush the edited state of our on-chip binding table to the pool.
Previously,
the CS will just normally consume this state. But when RS is enabled, it first
processes
this command before passing it to the CS ca
Update the on-chip binding table for every generated renderbuffer, constant,
and texture surface_state entries. When hw-generated binding-tables are enabled,
bspec dictates that surface state entries should aligned to a 64-byte boundary.
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i9
When surface_state pointing to pull constant surfaces are changed, update
on-chip binding table. Same with VS ubo surface states.
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/mesa/drivers
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/brw_defines.h |5 +
src/mesa/drivers/dri/i965/brw_state.h |6 ++
src/mesa/drivers/dri/i965/gen7_misc_state.c | 31 +++
3 files changed, 42 insertions(+)
diff --git a/src/mesa/drivers/
On Haswell hardware with resource streamer enabled, enable the on-chip hardware
binding tables. The hw-bt can be updated directly using EDIT commands.
Skip manual generation of binding tables when this is activated.
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/brw_context.c
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/brw_draw.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 5730eed..436077b 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b
Prior to changing the Surface State Base Address, the resouce streamer must be
disabled
within a batch buffer where the RS is enabled. RS is re-enabled again once the
SBA is updated.
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/brw_misc_state.c |7 +++
src/mesa/drivers
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 409df29..84736a8 100644
--- a/src/mesa/drivers/dri/i965/i
Signed-off-by: Abdiel Janulgue
---
src/mesa/drivers/dri/i965/intel_reg.h |4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_reg.h
b/src/mesa/drivers/dri/i965/intel_reg.h
index f45a8f3..2cf68dd 100644
--- a/src/mesa/drivers/dri/i965/intel_reg.h
+++ b/src/me
The following RFC patchset initially enables the resource streamer on
Haswell.
We can think of the resource streamer as a command streamer accelerator:
It accelerates certain commands that would normally take time to build-up
and submit to the GPU; hence reducing some of the overhead associated
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