Update the on-chip binding table for every generated renderbuffer, constant,
and texture surface_state entries. When hw-generated binding-tables are enabled,
bspec dictates that surface state entries should aligned to a 64-byte boundary.
Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 36 ++++++++++++++++++---
1 file changed, 31 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 99b00e3..6a8e1fd 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -244,7 +244,12 @@ gen7_update_buffer_texture_surface(struct gl_context *ctx,
gl_format format = tObj->_BufferObjectFormat;
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, &binding_table[surf_index]);
+ 8 * 4,
+ intel->is_haswell? 64 : 32,
+ &binding_table[surf_index]);
+ if (intel->is_haswell) {
+ gen7_update_ps_binding_table(brw, surf_index, binding_table[surf_index]);
+ }
memset(surf, 0, 8 * 4);
uint32_t surface_format = brw_format_for_mesa_format(format);
@@ -303,7 +308,15 @@ gen7_update_texture_surface(struct gl_context *ctx,
}
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, &binding_table[surf_index]);
+ 8 * 4,
+ intel->is_haswell? 64 : 32,
+ &binding_table[surf_index]);
+ if (intel->is_haswell) {
+ if (binding_table == brw->wm.surf_offset)
+ gen7_update_ps_binding_table(brw, surf_index,
binding_table[surf_index]);
+ if (binding_table == brw->vs.surf_offset)
+ gen7_update_vs_binding_table(brw, surf_index,
binding_table[surf_index]);
+ }
memset(surf, 0, 8 * 4);
uint32_t tex_format = translate_tex_format(intel,
@@ -394,7 +407,9 @@ gen7_create_constant_surface(struct brw_context *brw,
const GLint w = elements - 1;
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, out_offset);
+ 8 * 4,
+ intel->is_haswell? 64 : 32,
+ out_offset);
memset(surf, 0, 8 * 4);
surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
@@ -495,7 +510,13 @@ gen7_update_null_renderbuffer_surface(struct brw_context
*brw, unsigned unit)
const struct gl_framebuffer *fb = ctx->DrawBuffer;
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, &brw->wm.surf_offset[unit]);
+ 8 * 4,
+ intel->is_haswell? 64 : 32,
+ &brw->wm.surf_offset[unit]);
+
+ if (intel->is_haswell) {
+ gen7_update_ps_binding_table(brw, unit, brw->wm.surf_offset[unit]);
+ }
memset(surf, 0, 8 * 4);
/* From the Ivybridge PRM, Volume 4, Part 1, page 65,
@@ -538,7 +559,12 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 8 * 4, 32, &brw->wm.surf_offset[unit]);
+ 8 * 4,
+ intel->is_haswell? 64 : 32,
+ &brw->wm.surf_offset[unit]);
+ if (intel->is_haswell) {
+ gen7_update_ps_binding_table(brw, unit, brw->wm.surf_offset[unit]);
+ }
memset(surf, 0, 8 * 4);
intel_miptree_used_for_rendering(irb->mt);
--
1.7.9.5
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