[llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86AsmPrinter.cpp X86AsmPrinter.h X86ISelLowering.cpp X86IntelAsmPrinter.cpp X86TargetAsmInfo.cpp

Changes in directory llvm/lib/Target/X86: X86ATTAsmPrinter.cpp updated: 1.70 -> 1.71 X86AsmPrinter.cpp updated: 1.211 -> 1.212 X86AsmPrinter.h updated: 1.34 -> 1.35 X86ISelLowering.cpp updated: 1.283 -> 1.284 X86IntelAsmPrinter.cpp updated: 1.62 -> 1.63 X86TargetAsmInfo.cpp updated: 1.6 -> 1.7 -

[llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp DwarfWriter.cpp

Changes in directory llvm/lib/CodeGen: AsmPrinter.cpp updated: 1.114 -> 1.115 DwarfWriter.cpp updated: 1.89 -> 1.90 --- Log message: 1. Clean up code due to changes in SwitchTo*Section(2) 2. Added partial debug support for mingw\cygwin targets (the same as Linux\ELF). Please note, that curr

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

Changes in directory llvm/lib/Target/PowerPC: PPCAsmPrinter.cpp updated: 1.204 -> 1.205 --- Log message: 1. Clean up code due to changes in SwitchTo*Section(2) 2. Added partial debug support for mingw\cygwin targets (the same as Linux\ELF). Please note, that currently mingw\cygwin uses 'sta

[llvm-commits] CVS: llvm/test/Regression/CodeGen/ARM/alloca.ll

Changes in directory llvm/test/Regression/CodeGen/ARM: alloca.ll updated: 1.2 -> 1.3 --- Log message: add support for calling functions when the caller has variable sized objects --- Diffs of the changes: (+4 -1) alloca.ll |5 - 1 files changed, 4 insertions(+), 1 deletion(-) Ind

[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp

Changes in directory llvm/lib/Target/ARM: ARMRegisterInfo.cpp updated: 1.23 -> 1.24 --- Log message: add support for calling functions when the caller has variable sized objects --- Diffs of the changes: (+19 -1) ARMRegisterInfo.cpp | 20 +++- 1 files changed, 19 insertio

[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaBranchSelector.cpp Alpha.h AlphaISelLowering.cpp AlphaISelLowering.h AlphaInstrFormats.td AlphaInstrInfo.cpp AlphaInstrInfo.h AlphaInstrInfo.td AlphaTarg

Changes in directory llvm/lib/Target/Alpha: AlphaBranchSelector.cpp added (r1.1) Alpha.h updated: 1.7 -> 1.8 AlphaISelLowering.cpp updated: 1.70 -> 1.71 AlphaISelLowering.h updated: 1.21 -> 1.22 AlphaInstrFormats.td updated: 1.28 -> 1.29 AlphaInstrInfo.cpp updated: 1.11 -> 1.12 AlphaInstrInfo.h

[llvm-commits] CVS: llvm/lib/Transforms/Utils/LCSSA.cpp

Changes in directory llvm/lib/Transforms/Utils: LCSSA.cpp updated: 1.28 -> 1.29 --- Log message: Fix PR977: http://llvm.org/PR977 and Transforms/LCSSA/2006-10-31-UnreachableBlock.ll --- Diffs of the changes: (+8 -1) LCSSA.cpp |9 - 1 files changed, 8 insertions(+), 1 deletion

[llvm-commits] CVS: llvm/test/Regression/Transforms/LCSSA/2006-10-31-UnreachableBlock.ll

Changes in directory llvm/test/Regression/Transforms/LCSSA: 2006-10-31-UnreachableBlock.ll added (r1.1) --- Log message: testcase for PR977: http://llvm.org/PR977 --- Diffs of the changes: (+270 -0) 2006-10-31-UnreachableBlock.ll | 270 + 1 files c

[llvm-commits] CVS: llvm/test/Regression/Transforms/LCSSA/2006-10-31-UnreachableBlock-2.ll

Changes in directory llvm/test/Regression/Transforms/LCSSA: 2006-10-31-UnreachableBlock-2.ll added (r1.1) --- Log message: another testcase for PR977: http://llvm.org/PR977 --- Diffs of the changes: (+210 -0) 2006-10-31-UnreachableBlock-2.ll | 210 +++

[llvm-commits] CVS: llvm/lib/Transforms/Utils/LCSSA.cpp

Changes in directory llvm/lib/Transforms/Utils: LCSSA.cpp updated: 1.29 -> 1.30 --- Log message: generalize the fix for PR977: http://llvm.org/PR977 to also fix Transforms/LCSSA/2006-10-31-UnreachableBlock-2.ll --- Diffs of the changes: (+26 -28) LCSSA.cpp | 54

[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h

Changes in directory llvm/lib/Target/PowerPC: PPCISelLowering.cpp updated: 1.215 -> 1.216 PPCISelLowering.h updated: 1.52 -> 1.53 --- Log message: Change the prototype for TargetLowering::isOperandValidForConstraint --- Diffs of the changes: (+20 -12) PPCISelLowering.cpp | 29 +++

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.309 -> 1.310 --- Log message: TargetLowering::isOperandValidForConstraint --- Diffs of the changes: (+7 -2) SelectionDAGISel.cpp |9 +++-- 1 files changed, 7 insertions(+), 2 deletions(-) Index: l

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.284 -> 1.285 --- Log message: handle "st" as "st(0)" --- Diffs of the changes: (+12 -3) X86ISelLowering.cpp | 15 --- 1 files changed, 12 insertions(+), 3 deletions(-) Index: llvm/lib/Target/X86/X86ISe

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: TargetLowering.cpp updated: 1.77 -> 1.78 --- Log message: Change the prototype for TargetLowering::isOperandValidForConstraint --- Diffs of the changes: (+8 -5) TargetLowering.cpp | 13 - 1 files changed, 8 insertions(+), 5

[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h

Changes in directory llvm/include/llvm/Target: TargetLowering.h updated: 1.82 -> 1.83 --- Log message: Change the prototype for TargetLowering::isOperandValidForConstraint --- Diffs of the changes: (+6 -3) TargetLowering.h |9 ++--- 1 files changed, 6 insertions(+), 3 deletions(-)

[llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/add.ll mul5.ll s4addl.ll s4addq.ll

Changes in directory llvm/test/Regression/CodeGen/Alpha: add.ll added (r1.1) mul5.ll updated: 1.3 -> 1.4 s4addl.ll (r1.1) removed s4addq.ll (r1.5) removed --- Log message: make one giant add and sub tester --- Diffs of the changes: (+188 -0) add.ll | 183 ++

[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp AlphaInstrInfo.td

Changes in directory llvm/lib/Target/Alpha: AlphaISelDAGToDAG.cpp updated: 1.59 -> 1.60 AlphaInstrInfo.td updated: 1.131 -> 1.132 --- Log message: Let us play simplify the td file (and fix a few missed sub and mul patterns). --- Diffs of the changes: (+63 -83) AlphaISelDAGToDAG.cpp |8 +

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAG.cpp updated: 1.104 -> 1.105 --- Log message: handle global address constant sdnodes --- Diffs of the changes: (+7 -2) ScheduleDAG.cpp |9 +++-- 1 files changed, 7 insertions(+), 2 deletions(-) Index: llvm/lib/CodeGen

[llvm-commits] CVS: llvm/test/Regression/CodeGen/X86/asm-global-imm.ll

Changes in directory llvm/test/Regression/CodeGen/X86: asm-global-imm.ll added (r1.1) --- Log message: new testcase for PR882: http://llvm.org/PR882 --- Diffs of the changes: (+29 -0) asm-global-imm.ll | 29 + 1 files changed, 29 insertions(+) Index: llvm/t

[llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp

Changes in directory llvm/lib/Target/X86: X86ATTAsmPrinter.cpp updated: 1.71 -> 1.72 --- Log message: implement the 'c' inline asm modifier character --- Diffs of the changes: (+3 -0) X86ATTAsmPrinter.cpp |3 +++ 1 files changed, 3 insertions(+) Index: llvm/lib/Target/X86/X86ATTAsmPr

[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h

Changes in directory llvm/lib/Target/X86: X86ISelLowering.cpp updated: 1.285 -> 1.286 X86ISelLowering.h updated: 1.77 -> 1.78 --- Log message: allow the address of a global to be used with the "i" constraint when in -static mode. This implements PR882: http://llvm.org/PR882 . --- Diffs of th

[llvm-commits] CVS: llvm/lib/Target/X86/X86AsmPrinter.cpp

Changes in directory llvm/lib/Target/X86: X86AsmPrinter.cpp updated: 1.212 -> 1.213 --- Log message: Nuke dead code. --- Diffs of the changes: (+0 -1) X86AsmPrinter.cpp |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/Target/X86/X86AsmPrinter.cpp diff -u llvm/lib/Target/X86/X86Asm

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.310 -> 1.311 --- Log message: look through isunordered to inline it into branch blocks. --- Diffs of the changes: (+43 -12) SelectionDAGISel.cpp | 55 +++

[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/fp-branch.ll

Changes in directory llvm/test/Regression/CodeGen/PowerPC: fp-branch.ll added (r1.1) --- Log message: This test should compile down to one comparison, not two. --- Diffs of the changes: (+20 -0) fp-branch.ll | 20 1 files changed, 20 insertions(+) Index: llvm/test/

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAGISel.cpp updated: 1.311 -> 1.312 --- Log message: Compile CodeGen/PowerPC/fp-branch.ll to: _intcoord_cond_next55: LBB1_3: ;cond_next55 lis r2, ha16(LCPI1_0) lfs f0, lo16(LCPI1_0)(r2) fcmpu cr0, f1, f0

[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp AlphaInstrInfo.cpp AlphaInstrInfo.td AlphaLLRP.cpp AlphaRegisterInfo.cpp

Changes in directory llvm/lib/Target/Alpha: AlphaISelDAGToDAG.cpp updated: 1.60 -> 1.61 AlphaInstrInfo.cpp updated: 1.12 -> 1.13 AlphaInstrInfo.td updated: 1.132 -> 1.133 AlphaLLRP.cpp updated: 1.2 -> 1.3 AlphaRegisterInfo.cpp updated: 1.48 -> 1.49 --- Log message: more shotenning --- Diffs of

[llvm-commits] CVS: llvm/lib/Target/Target.td

Changes in directory llvm/lib/Target: Target.td updated: 1.86 -> 1.87 --- Log message: Add constraints to Instruction class. --- Diffs of the changes: (+2 -0) Target.td |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/Target.td diff -u llvm/lib/Target/Target.td:1.86 llvm

[llvm-commits] CVS: llvm/utils/TableGen/CodeGenInstruction.h CodeGenTarget.cpp DAGISelEmitter.cpp InstrInfoEmitter.cpp InstrInfoEmitter.h

Changes in directory llvm/utils/TableGen: CodeGenInstruction.h updated: 1.19 -> 1.20 CodeGenTarget.cpp updated: 1.69 -> 1.70 DAGISelEmitter.cpp updated: 1.272 -> 1.273 InstrInfoEmitter.cpp updated: 1.45 -> 1.46 InstrInfoEmitter.h updated: 1.12 -> 1.13 --- Log message: Add operand constraints to

[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp

Changes in directory llvm/utils/TableGen: DAGISelEmitter.cpp updated: 1.273 -> 1.274 --- Log message: Not meant to be checked in. --- Diffs of the changes: (+1 -5) DAGISelEmitter.cpp |6 +- 1 files changed, 1 insertion(+), 5 deletions(-) Index: llvm/utils/TableGen/DAGISelEmitter.c

[llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h

Changes in directory llvm/include/llvm/Target: TargetInstrInfo.h updated: 1.99 -> 1.100 --- Log message: Add operand constraints to TargetInstrInfo. --- Diffs of the changes: (+21 -0) TargetInstrInfo.h | 21 + 1 files changed, 21 insertions(+) Index: llvm/include/llv

[llvm-commits] CVS: llvm/lib/CodeGen/BranchFolding.cpp

Changes in directory llvm/lib/CodeGen: BranchFolding.cpp updated: 1.27 -> 1.28 --- Log message: enable branch folding with an option --- Diffs of the changes: (+2 -1) BranchFolding.cpp |3 ++- 1 files changed, 2 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/BranchFolding.cpp d

[llvm-commits] [llvm-gcc] REM patch for llvm-gcc

Attached is the corresponding llvm-gcc patch for the LLVM REM patch. This makes llvm-gcc generate [us]rem instructions instead of just rem. Reid. Index: gcc/llvm-convert.cpp === --- gcc/llvm-convert.cpp (revision 193) +++ gcc/llvm-con

[llvm-commits] CVS: llvm/lib/CodeGen/BranchFolding.cpp

Changes in directory llvm/lib/CodeGen: BranchFolding.cpp updated: 1.28 -> 1.29 --- Log message: make tail merging more aggressive. If two blocks share a common tail, but the tail is not an entire block for either of them, pick one, split it, then merge the common part. --- Diffs of the chan

[llvm-commits] CVS: llvm-test/Makefile.programs

Changes in directory llvm-test: Makefile.programs updated: 1.234 -> 1.235 --- Log message: switch llcbeta back to tail merging --- Diffs of the changes: (+4 -2) Makefile.programs |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) Index: llvm-test/Makefile.programs diff -u ll

[llvm-commits] CVS: llvm/lib/ExecutionEngine/Interpreter/Execution.cpp

Changes in directory llvm/lib/ExecutionEngine/Interpreter: Execution.cpp updated: 1.141 -> 1.142 --- Log message: Fix a bug in the interpreter where divides of unmatched signed operands would fail. E.g. udiv sint X, Y or sdiv uint X, Y would fail to find a type match in the switch statement an

[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp SelectionDAGPrinter.cpp

Changes in directory llvm/lib/CodeGen/SelectionDAG: SelectionDAG.cpp updated: 1.363 -> 1.364 SelectionDAGPrinter.cpp updated: 1.41 -> 1.42 --- Log message: Print jumptable index. --- Diffs of the changes: (+4 -0) SelectionDAG.cpp|2 ++ SelectionDAGPrinter.cpp |2 ++ 2 files

[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp

Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.529 -> 1.530 --- Log message: Fold things like "phi [add (a,b), add(c,d)]" into two phi's and one add. This triggers thousands of times on multisource. --- Diffs of the changes: (+57 -3) InstructionCombi

[llvm-commits] CVS: llvm/lib/ExecutionEngine/Interpreter/Execution.cpp

Changes in directory llvm/lib/ExecutionEngine/Interpreter: Execution.cpp updated: 1.142 -> 1.143 --- Log message: Remove unnecessary sign conversions made possible by last patch. --- Diffs of the changes: (+0 -4) Execution.cpp |4 1 files changed, 4 deletions(-) Index: llvm/lib/

[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp

Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.530 -> 1.531 --- Log message: Fix a bug in the previous patch --- Diffs of the changes: (+6 -3) InstructionCombining.cpp |9 ++--- 1 files changed, 6 insertions(+), 3 deletions(-) Index: llvm/lib

[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td

Changes in directory llvm/lib/Target/X86: X86InstrSSE.td updated: 1.167 -> 1.168 --- Log message: Fix ldmxcsr JIT encoding. --- Diffs of the changes: (+4 -6) X86InstrSSE.td | 10 -- 1 files changed, 4 insertions(+), 6 deletions(-) Index: llvm/lib/Target/X86/X86InstrSSE.td diff -

[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp

Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.531 -> 1.532 --- Log message: Turn a phi of many loads into a phi of the address and a single load of the result. This can significantly shrink code and exposes identities more aggressively. --- Diffs of th

[llvm-commits] CVS: llvm/test/Regression/Transforms/InstCombine/load.ll

Changes in directory llvm/test/Regression/Transforms/InstCombine: load.ll updated: 1.11 -> 1.12 --- Log message: remove a testcase for a marginal feature --- Diffs of the changes: (+0 -14) load.ll | 14 -- 1 files changed, 14 deletions(-) Index: llvm/test/Regression/Transfo

[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp

Changes in directory llvm/lib/Transforms/Scalar: InstructionCombining.cpp updated: 1.532 -> 1.533 --- Log message: Factor gep instructions through phi nodes. --- Diffs of the changes: (+39 -10) InstructionCombining.cpp | 49 +-- 1 files changed