[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2007-05-05 Thread Chris Lattner
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.49 -> 1.50 --- Log message: implement anyextend from i1 -> i64 --- Diffs of the changes: (+2 -0) IA64InstrInfo.td |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/IA64/IA64InstrInfo.td diff -u llvm/l

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2006-07-31 Thread Evan Cheng
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.47 -> 1.48 --- Log message: Remove a duplicate pattern. --- Diffs of the changes: (+0 -1) IA64InstrInfo.td |1 - 1 files changed, 1 deletion(-) Index: llvm/lib/Target/IA64/IA64InstrInfo.td diff -u llvm/lib/Target/I

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2006-03-07 Thread Duraid Madina
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.46 -> 1.47 --- Log message: doo de doo --- Diffs of the changes: (+158 -148) IA64InstrInfo.td | 306 --- 1 files changed, 158 insertions(+), 148 deletions(-) Index

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2006-02-10 Thread Duraid Madina
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.45 -> 1.46 --- Log message: now short immediates will get matched (previously constants were all triggering movl 64bit imm fat instructions) --- Diffs of the changes: (+3 -5) IA64InstrInfo.td |8 +++- 1 files

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2006-01-19 Thread Duraid Madina
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.39 -> 1.40 --- Log message: fix boolean XOR (which fixes up comparisons..) --- Diffs of the changes: (+4 -1) IA64InstrInfo.td |5 - 1 files changed, 4 insertions(+), 1 deletion(-) Index: llvm/lib/Target/IA64

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td IA64RegisterInfo.cpp IA64RegisterInfo.td

2006-01-16 Thread Duraid Madina
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.38 -> 1.39 IA64RegisterInfo.cpp updated: 1.9 -> 1.10 IA64RegisterInfo.td updated: 1.12 -> 1.13 --- Log message: use proper (82-bit) spills/fills when spilling FP regs, so that divides don't get broken. this fixes obsequi, s

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2006-01-10 Thread Duraid Madina
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.36 -> 1.37 --- Log message: this just might work --- Diffs of the changes: (+4 -4) IA64InstrInfo.td |8 1 files changed, 4 insertions(+), 4 deletions(-) Index: llvm/lib/Target/IA64/IA64InstrInfo.td diff

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2006-01-10 Thread Duraid Madina
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.35 -> 1.36 --- Log message: add support for selecting bools FIXME: this is commented out because it makes tblgen go a bit fruity --- Diffs of the changes: (+5 -1) IA64InstrInfo.td |6 +- 1 files changed, 5 ins

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2005-12-26 Thread Evan Cheng
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.34 -> 1.35 --- Log message: Added field noResults to Instruction. Currently tblgen cannot tell which operands in the operand list are results so it assumes the first one is a result. This is bad. Ideally we would fix this by

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2005-12-25 Thread Duraid Madina
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.33 -> 1.34 --- Log message: we don't feed our call instructions extra operands --- Diffs of the changes: (+3 -3) IA64InstrInfo.td |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) Index: llvm/lib/Target/

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2005-12-21 Thread Duraid Madina
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.32 -> 1.33 --- Log message: oops, back this out --- Diffs of the changes: (+2 -3) IA64InstrInfo.td |5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) Index: llvm/lib/Target/IA64/IA64InstrInfo.td diff -u l

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2005-12-21 Thread Duraid Madina
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.31 -> 1.32 --- Log message: we need to emit the getf.d instruction in lowering, so add it to IA64ISD --- Diffs of the changes: (+11 -2) IA64InstrInfo.td | 13 +++-- 1 files changed, 11 insertions(+), 2 delet

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2005-12-04 Thread Chris Lattner
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.29 -> 1.30 --- Log message: Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted. --- Diffs of the changes: (+6 -6) IA64InstrInfo.td

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2005-11-13 Thread Duraid Madina
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.28 -> 1.29 --- Log message: add FP select. next up - divide! --- Diffs of the changes: (+5 -3) IA64InstrInfo.td |8 +--- 1 files changed, 5 insertions(+), 3 deletions(-) Index: llvm/lib/Target/IA64/IA64InstrI

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2005-11-03 Thread Duraid Madina
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.27 -> 1.28 --- Log message: fun with predicates! (add TRUNC i64->i1, AND i1 i1, fix XOR i1 i1) --- Diffs of the changes: (+97 -41) IA64InstrInfo.td | 137 ++- 1 file

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2005-11-03 Thread Duraid Madina
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.26 -> 1.27 --- Log message: add pattern to load constant 0 into a predicate reg --- Diffs of the changes: (+2 -0) IA64InstrInfo.td |2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/IA64/IA64InstrInfo

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2005-11-02 Thread Chris Lattner
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.25 -> 1.26 --- Log message: Fix a bug that prevented this pattern from matching --- Diffs of the changes: (+1 -1) IA64InstrInfo.td |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/Target/IA64/

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2005-11-01 Thread Chris Lattner
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.24 -> 1.25 --- Log message: This works now --- Diffs of the changes: (+1 -2) IA64InstrInfo.td |3 +-- 1 files changed, 1 insertion(+), 2 deletions(-) Index: llvm/lib/Target/IA64/IA64InstrInfo.td diff -u llvm/lib/T

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2005-11-01 Thread Duraid Madina
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.23 -> 1.24 --- Log message: add support for SELECT to TargetSelectionDAG.td, add support for selecting ints to IA64, and a few other ia64 bits and pieces --- Diffs of the changes: (+38 -31) IA64InstrInfo.td | 69

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2005-10-31 Thread Duraid Madina
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.22 -> 1.23 --- Log message: so tablegen was thinking I might want to convert FPs to predicates. clever little tablegen! --- Diffs of the changes: (+3 -4) IA64InstrInfo.td |7 +++ 1 files changed, 3 insertions(

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2005-10-31 Thread Duraid Madina
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.21 -> 1.22 --- Log message: add support for int->FP and FP->int ops, and add ia64 patterns for these --- Diffs of the changes: (+12 -0) IA64InstrInfo.td | 12 1 files changed, 12 insertions(+) Index:

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2005-10-31 Thread Duraid Madina
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.20 -> 1.21 --- Log message: add zeroextend predicate->integer --- Diffs of the changes: (+42 -37) IA64InstrInfo.td | 79 +-- 1 files changed, 42 insertions(+), 37 d

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2005-10-30 Thread Duraid Madina
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.18 -> 1.19 --- Log message: fix some broken comparisons, this affected the Pattern isel too. --- Diffs of the changes: (+4 -27) IA64InstrInfo.td | 31 --- 1 files changed, 4 insertions(+),

[llvm-commits] CVS: llvm/lib/Target/IA64/IA64InstrInfo.td

2005-10-28 Thread Duraid Madina
Changes in directory llvm/lib/Target/IA64: IA64InstrInfo.td updated: 1.16 -> 1.17 --- Log message: add shladd --- Diffs of the changes: (+42 -42) IA64InstrInfo.td | 84 +++ 1 files changed, 42 insertions(+), 42 deletions(-) Index: ll