Changes in directory llvm/lib/Target/IA64:
IA64InstrInfo.td updated: 1.26 -> 1.27 --- Log message: add pattern to load constant 0 into a predicate reg --- Diffs of the changes: (+2 -0) IA64InstrInfo.td | 2 ++ 1 files changed, 2 insertions(+) Index: llvm/lib/Target/IA64/IA64InstrInfo.td diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.26 llvm/lib/Target/IA64/IA64InstrInfo.td:1.27 --- llvm/lib/Target/IA64/IA64InstrInfo.td:1.26 Wed Nov 2 23:45:34 2005 +++ llvm/lib/Target/IA64/IA64InstrInfo.td Thu Nov 3 04:09:32 2005 @@ -361,6 +361,8 @@ def : Pat<(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm)>; def : Pat<(i64 imm64:$imm), (MOVL imm64:$imm)>; def : Pat<(i1 -1), (CMPEQ r0, r0)>; // TODO: this should just be a ref to p0 +def : Pat<(i1 0), (CMPNE r0, r0)>; // TODO: any instruction actually *using* + // this predicate should be killed! // TODO: support postincrement (reg, imm9) loads+stores - this needs more // tablegen support _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
