Changes in directory llvm/lib/Target/IA64:
IA64InstrInfo.td updated: 1.29 -> 1.30 --- Log message: Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted. --- Diffs of the changes: (+6 -6) IA64InstrInfo.td | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) Index: llvm/lib/Target/IA64/IA64InstrInfo.td diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.29 llvm/lib/Target/IA64/IA64InstrInfo.td:1.30 --- llvm/lib/Target/IA64/IA64InstrInfo.td:1.29 Sun Nov 13 19:17:30 2005 +++ llvm/lib/Target/IA64/IA64InstrInfo.td Sun Dec 4 20:34:29 2005 @@ -156,31 +156,31 @@ def MIX1L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), "mix1.l $dst = $src1, $src2;;", [(set GR:$dst, (or (and GR:$src1, isMIX1Lable), - (and (srl GR:$src2, 8), isMIX1Lable)))]>; + (and (srl GR:$src2, (i64 8)), isMIX1Lable)))]>; def MIX2L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), "mix2.l $dst = $src1, $src2;;", [(set GR:$dst, (or (and GR:$src1, isMIX2Lable), - (and (srl GR:$src2, 16), isMIX2Lable)))]>; + (and (srl GR:$src2, (i64 16)), isMIX2Lable)))]>; def MIX4L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), "mix4.l $dst = $src1, $src2;;", [(set GR:$dst, (or (and GR:$src1, isMIX4Lable), - (and (srl GR:$src2, 32), isMIX4Lable)))]>; + (and (srl GR:$src2, (i64 32)), isMIX4Lable)))]>; def MIX1R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), "mix1.r $dst = $src1, $src2;;", - [(set GR:$dst, (or (and (shl GR:$src1, 8), isMIX1Rable), + [(set GR:$dst, (or (and (shl GR:$src1, (i64 8)), isMIX1Rable), (and GR:$src2, isMIX1Rable)))]>; def MIX2R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), "mix2.r $dst = $src1, $src2;;", - [(set GR:$dst, (or (and (shl GR:$src1, 16), isMIX2Rable), + [(set GR:$dst, (or (and (shl GR:$src1, (i64 16)), isMIX2Rable), (and GR:$src2, isMIX2Rable)))]>; def MIX4R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), "mix4.r $dst = $src1, $src2;;", - [(set GR:$dst, (or (and (shl GR:$src1, 32), isMIX4Rable), + [(set GR:$dst, (or (and (shl GR:$src1, (i64 32)), isMIX4Rable), (and GR:$src2, isMIX4Rable)))]>; def GETFSIGD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, FP:$src), _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits