Changes in directory llvm/docs:
ReleaseNotes.html updated: 1.348 -> 1.349
---
Log message:
Add some more notes, many still missing
---
Diffs of the changes: (+31 -2)
ReleaseNotes.html | 33 +++--
1 files changed, 31 insertions(+), 2 deletions(-)
Index: llvm
Changes in directory llvm/projects/sample/autoconf:
AutoRegen.sh updated: 1.2 -> 1.3
configure.ac updated: 1.4 -> 1.5
---
Log message:
Have the AutoRegen.sh script prompt the user for the LLVM src and obj
directories if it can't find them. Then, replace those values into the
configure.ac scrip
Changes in directory llvm/autoconf/m4:
config_project.m4 updated: 1.1 -> 1.2
---
Log message:
Make it possible to default the llvm_src and llvm_obj variables based on
the arguments to the macro. This better supports the AutoRegen.sh script
in projects/sample/autoconf.
---
Diffs of the changes
Changes in directory llvm/docs:
ReleaseNotes.html updated: 1.347 -> 1.348
---
Log message:
add a bunch of stuff, pieces still missing
---
Diffs of the changes: (+171 -47)
ReleaseNotes.html | 218 ++
1 files changed, 171 insertions(+), 47
Changes in directory llvm/tools/llc:
llc.cpp updated: 1.129 -> 1.130
---
Log message:
Add a warning.
---
Diffs of the changes: (+3 -0)
llc.cpp |3 +++
1 files changed, 3 insertions(+)
Index: llvm/tools/llc/llc.cpp
diff -u llvm/tools/llc/llc.cpp:1.129 llvm/tools/llc/llc.cpp:1.130
---
Changes in directory llvm/tools/llvm-db:
llvm-db.cpp updated: 1.9 -> 1.10
---
Log message:
Add a warning
---
Diffs of the changes: (+1 -0)
llvm-db.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/tools/llvm-db/llvm-db.cpp
diff -u llvm/tools/llvm-db/llvm-db.cpp:1.9 llvm/tools/llv
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.163 -> 1.164
---
Log message:
Use vmladduhm to do v8i16 multiplies which is faster and simpler than doing
even/odd halves. Thanks to Nate telling me what's what.
---
Diffs of the changes: (+3 -18)
PPCISelLowerin
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.162 -> 1.163
README_ALTIVEC.txt updated: 1.27 -> 1.28
---
Log message:
Implement v16i8 multiply with this code:
vmuloub v5, v3, v2
vmuleub v2, v3, v2
vperm v2, v2, v5, v4
This implements CodeG
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
vec_mul.ll updated: 1.1 -> 1.2
---
Log message:
Add tests for v8i16 and v16i8
---
Diffs of the changes: (+16 -2)
vec_mul.ll | 18 --
1 files changed, 16 insertions(+), 2 deletions(-)
Index: llvm/test/Regression/
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.91 -> 1.92
---
Log message:
Correct comments
---
Diffs of the changes: (+6 -6)
README.txt | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.161 -> 1.162
---
Log message:
Lower v8i16 multiply into this code:
li r5, lo16(LCPI1_0)
lis r6, ha16(LCPI1_0)
lvx v4, r6, r5
vmulouh v5, v3, v2
vmuleuh v2, v3, v2
vperm
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.160 -> 1.161
---
Log message:
Custom lower v4i32 multiplies into a cute sequence, instead of having legalize
scalarize the sequence into 4 mullw's and a bunch of load/store traffic.
This speeds up v4i32 multiplies 4.1
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
vec_mul.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+11 -0)
vec_mul.ll | 11 +++
1 files changed, 11 insertions(+)
Index: llvm/test/Regression/CodeGen/PowerPC/vec_mul.ll
diff -c /dev/null ll
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.90 -> 1.91
---
Log message:
Another entry
---
Diffs of the changes: (+35 -0)
README.txt | 35 +++
1 files changed, 35 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Targ
Changes in directory llvm/utils/PerfectShuffle:
PerfectShuffle.cpp updated: 1.6 -> 1.7
---
Log message:
Fix a build failure on Vladimir's tester.
---
Diffs of the changes: (+1 -0)
PerfectShuffle.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/utils/PerfectShuffle/PerfectShuffle
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.89 -> 1.90
---
Log message:
Another entry.
---
Diffs of the changes: (+151 -0)
README.txt | 151 +
1 files changed, 151 insertions(+)
Index: llvm/lib/Target/X86/RE
Changes in directory llvm-test/autoconf:
configure.ac updated: 1.31 -> 1.32
---
Log message:
Added nurbs as an external test.
---
Diffs of the changes: (+1 -0)
configure.ac |1 +
1 files changed, 1 insertion(+)
Index: llvm-test/autoconf/configure.ac
diff -u llvm-test/autoconf/configu
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.172 -> 1.173
X86InstrSSE.td updated: 1.99 -> 1.100
---
Log message:
Use movss to insert_vector_elt(v, s, 0).
---
Diffs of the changes: (+37 -19)
X86ISelLowering.cpp | 51 -
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.468 -> 1.469
---
Log message:
Turn x86 unaligned load/store intrinsics into aligned load/store instructions
if the pointer is known aligned.
---
Diffs of the changes: (+16 -1)
InstructionCombining.cpp |
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.367 -> 1.368
---
Log message:
Fix handling of calls in functions that use vectors. This fixes a crash on
the code in GCC PR26546: http://llvm.cs.uiuc.edu/PR26546 .
---
Diffs of the changes: (+1 -13)
LegalizeDAG
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.171 -> 1.172
---
Log message:
Use two pinsrw to insert an element into v4i32 / v4f32 vector.
---
Diffs of the changes: (+30 -3)
X86ISelLowering.cpp | 33 ++---
1 files changed, 30 insertio
Changes in directory llvm/lib/Target/PowerPC:
README_ALTIVEC.txt updated: 1.26 -> 1.27
---
Log message:
remove done item
---
Diffs of the changes: (+2 -19)
README_ALTIVEC.txt | 21 ++---
1 files changed, 2 insertions(+), 19 deletions(-)
Index: llvm/lib/Target/PowerPC/RE
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
vec_vrsave.ll added (r1.1)
---
Log message:
New testcase, shouldn't touch vrsave
---
Diffs of the changes: (+7 -0)
vec_vrsave.ll |7 +++
1 files changed, 7 insertions(+)
Index: llvm/test/Regression/CodeGen/PowerPC/vec_vrs
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.60 -> 1.61
---
Log message:
Don't diddle VRSAVE if no registers need to be added/removed from it. This
allows us to codegen functions as:
_test_rol:
vspltisw v2, -12
vrlw v2, v2, v2
blr
inste
Changes in directory llvm/include/llvm/CodeGen:
MachineInstr.h updated: 1.165 -> 1.166
---
Log message:
Add some convenience methods.
---
Diffs of the changes: (+10 -0)
MachineInstr.h | 10 ++
1 files changed, 10 insertions(+)
Index: llvm/include/llvm/CodeGen/MachineInstr.h
dif
Changes in directory llvm/lib/CodeGen:
MachineInstr.cpp updated: 1.107 -> 1.108
---
Log message:
Add a MachineInstr::eraseFromParent convenience method.
---
Diffs of the changes: (+9 -0)
MachineInstr.cpp |9 +
1 files changed, 9 insertions(+)
Index: llvm/lib/CodeGen/MachineIn
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.98 -> 1.99
---
Log message:
Encoding bug
---
Diffs of the changes: (+1 -1)
X86InstrSSE.td |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.59 -> 1.60
---
Log message:
Vectors that are known live-in and live-out are clearly already marked in
the vrsave register for the caller. This allows us to codegen a function as:
_test_rol:
mfspr r2, 256
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.td updated: 1.33 -> 1.34
---
Log message:
Prefer to allocate V2-V5 before V0,V1. This lets us generate code like this:
vspltisw v2, -12
vrlw v2, v2, v2
instead of:
vspltisw v0, -12
vrlw v2, v0, v0
Changes in directory llvm/lib/Target/PowerPC:
PPCCodeEmitter.cpp updated: 1.49 -> 1.50
PPCRegisterInfo.cpp updated: 1.58 -> 1.59
PPCRegisterInfo.h updated: 1.13 -> 1.14
---
Log message:
Move some knowledge about registers out of the code emitter into the register
info.
---
Diffs of the chang
Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.cpp updated: 1.57 -> 1.58
---
Log message:
Use a small table instead of macros to do this conversion.
---
Diffs of the changes: (+13 -10)
PPCRegisterInfo.cpp | 23 +--
1 files changed, 13 insertions(+), 10
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.170 -> 1.171
---
Log message:
Implement v8i16, v16i8 splat using unpckl + pshufd.
---
Diffs of the changes: (+56 -16)
X86ISelLowering.cpp | 72
1 files changed, 56
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.169 -> 1.170
---
Log message:
implement returns of a vector, testcase here: CodeGen/X86/vec_return.ll
---
Diffs of the changes: (+27 -23)
X86ISelLowering.cpp | 50 +++---
Changes in directory llvm/test/Regression/CodeGen/X86:
vec_return.ll added (r1.1)
---
Log message:
New testcase
---
Diffs of the changes: (+5 -0)
vec_return.ll |5 +
1 files changed, 5 insertions(+)
Index: llvm/test/Regression/CodeGen/X86/vec_return.ll
diff -c /dev/null llvm/test
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.366 -> 1.367
---
Log message:
Codegen insertelement with constant insertion points as scalar_to_vector
and a shuffle. For this:
void %test2(<4 x float>* %F, float %f) {
%tmp = load <4 x float>* %F
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.159 -> 1.160
---
Log message:
Make sure to check splats of every constant we can, handle splat(31) by
being a bit more clever, add support for odd splats from -31 to -17.
---
Diffs of the changes: (+14 -5)
PPCISel
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.139 -> 1.140
---
Log message:
Incorrect foldMemoryOperand entries
---
Diffs of the changes: (+6 -12)
X86RegisterInfo.cpp | 18 ++
1 files changed, 6 insertions(+), 12 deletions(-)
Index: llvm/lib/Ta
Changes in directory llvm/lib/Target/X86:
X86InstrSSE.td updated: 1.97 -> 1.98
---
Log message:
Errors in patterns preventing load folding
---
Diffs of the changes: (+16 -16)
X86InstrSSE.td | 32
1 files changed, 16 insertions(+), 16 deletions(-)
Index:
Changes in directory llvm/lib/Target/CBackend:
Writer.cpp updated: 1.259 -> 1.260
---
Log message:
Add checks for __OpenBSD__.
---
Diffs of the changes: (+1 -1)
Writer.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/CBackend/Writer.cpp
diff -u llvm/lib
Changes in directory llvm-test/SingleSource/Regression/C:
2004-08-12-InlinerAndAllocas.c updated: 1.4 -> 1.5
---
Log message:
Add checks for __OpenBSD__.
---
Diffs of the changes: (+1 -1)
2004-08-12-InlinerAndAllocas.c |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm-
Changes in directory llvm-test/MultiSource/Benchmarks/MallocBench/make:
arscan.c updated: 1.4 -> 1.5
job.c updated: 1.4 -> 1.5
make.h updated: 1.4 -> 1.5
misc.c updated: 1.4 -> 1.5
read.c updated: 1.5 -> 1.6
---
Log message:
Add checks for __OpenBSD__.
---
Diffs of the changes: (+11 -8)
ars
Changes in directory llvm/lib/System:
Mutex.cpp updated: 1.6 -> 1.7
---
Log message:
Add checks for __OpenBSD__.
---
Diffs of the changes: (+1 -1)
Mutex.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/System/Mutex.cpp
diff -u llvm/lib/System/Mutex.cpp:1.6 llv
Changes in directory llvm-test/SingleSource/Benchmarks/Misc:
mandel.c updated: 1.10 -> 1.11
---
Log message:
Add checks for __OpenBSD__.
---
Diffs of the changes: (+1 -1)
mandel.c |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm-test/SingleSource/Benchmarks/Misc/mande
Changes in directory llvm-test/MultiSource/Benchmarks/Olden/voronoi:
newvor.c updated: 1.10 -> 1.11
---
Log message:
Add checks for __OpenBSD__.
---
Diffs of the changes: (+1 -1)
newvor.c |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm-test/MultiSource/Benchmarks/Old
Changes in directory llvm-test/MultiSource/Applications/hexxagon:
hexxagonmove.cpp updated: 1.3 -> 1.4
---
Log message:
Add checks for __OpenBSD__.
---
Diffs of the changes: (+1 -1)
hexxagonmove.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm-test/MultiSource/App
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.158 -> 1.159
---
Log message:
Teach the ppc backend to use rol and vsldoi to generate splatted constants.
This implements vec_constants.ll:test_vsldoi and test_rol
---
Diffs of the changes: (+49 -15)
PPCISelLoweri
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
vec_constants.ll updated: 1.4 -> 1.5
---
Log message:
Some more cases that can be generated with two instructions
---
Diffs of the changes: (+9 -0)
vec_constants.ll |9 +
1 files changed, 9 insertions(+)
Index: llvm/t
Changes in directory llvm/lib/Target/PowerPC:
README_ALTIVEC.txt updated: 1.25 -> 1.26
---
Log message:
add a note
---
Diffs of the changes: (+10 -0)
README_ALTIVEC.txt | 10 ++
1 files changed, 10 insertions(+)
Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib
Changes in directory llvm-test:
Makefile.config.in updated: 1.19 -> 1.20
configure updated: 1.32 -> 1.33
---
Log message:
Added Nurbs external test.
---
Diffs of the changes: (+55 -1)
Makefile.config.in |4
configure | 52 +
Changes in directory llvm-test/External/Nurbs:
Makefile added (r1.1)
README added (r1.1)
---
Log message:
Initial commit of Nurbs as an External test.
---
Diffs of the changes: (+16 -0)
Makefile | 14 ++
README |2 ++
2 files changed, 16 insertions(+)
Index: llvm-test/
Changes in directory llvm-test/External/Nurbs:
---
Log message:
Directory /var/cvs/llvm/llvm-test/External/Nurbs added to the repository
---
Diffs of the changes: (+0 -0)
0 files changed
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h
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.168 -> 1.169
---
Log message:
FP SETOLT, SETOLT, SETUGE, SETUGT conditions were implemented incorrectly
---
Diffs of the changes: (+4 -4)
X86ISelLowering.cpp |8
1 files changed, 4 insertions(+), 4 deletio
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