[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCRegisterInfo.cpp updated: 1.59 -> 1.60
---
Log message:

Vectors that are known live-in and live-out are clearly already marked in 
the vrsave register for the caller.  This allows us to codegen a function as:

_test_rol:
        mfspr r2, 256
        mr r3, r2
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r3
        vspltisw v2, -12
        vrlw v2, v2, v2
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
        blr

instead of:

_test_rol:
        mfspr r2, 256
        oris r3, r2, 40960
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r3
        vspltisw v0, -12
        vrlw v2, v0, v0
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
        blr



---
Diffs of the changes:  (+16 -0)

 PPCRegisterInfo.cpp |   16 ++++++++++++++++
 1 files changed, 16 insertions(+)


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.59 
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.60
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.59    Mon Apr 17 16:07:20 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Apr 17 16:22:06 2006
@@ -355,6 +355,22 @@
     if (UsedRegs[VRRegNo[i]])
       UsedRegMask |= 1 << (31-i);
   
+  // Live in and live out values already must be in the mask, so don't bother
+  // marking them.
+  MachineFunction *MF = MI->getParent()->getParent();
+  for (MachineFunction::livein_iterator I = 
+       MF->livein_begin(), E = MF->livein_end(); I != E; ++I) {
+    unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
+    if (VRRegNo[RegNo] == I->first)        // If this really is a vector reg.
+      UsedRegMask &= ~(1 << (31-RegNo));   // Doesn't need to be marked.
+  }
+  for (MachineFunction::liveout_iterator I = 
+       MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) {
+    unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
+    if (VRRegNo[RegNo] == *I)              // If this really is a vector reg.
+      UsedRegMask &= ~(1 << (31-RegNo));   // Doesn't need to be marked.
+  }
+  
   unsigned SrcReg = MI->getOperand(1).getReg();
   unsigned DstReg = MI->getOperand(0).getReg();
   // If no registers are used, turn this into a copy.



_______________________________________________
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits