Changes in directory llvm/lib/Target/PowerPC:
PPCRegisterInfo.td updated: 1.33 -> 1.34
---
Log message:
Prefer to allocate V2-V5 before V0,V1. This lets us generate code like this:
vspltisw v2, -12
vrlw v2, v2, v2
instead of:
vspltisw v0, -12
vrlw v2, v0, v0
when a function is returning a value.
---
Diffs of the changes: (+1 -1)
PPCRegisterInfo.td | 2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.td
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.33
llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.34
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.td:1.33 Sat Mar 25 01:36:56 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td Mon Apr 17 16:19:12 2006
@@ -260,7 +260,7 @@
F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
- [V0, V1, V2, V3, V4, V5,
+ [V2, V3, V4, V5, V0, V1,
V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21,
V22, V23, V24, V25, V26, V27, V28, V29, V30, V31]>;
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