Changes in directory llvm/lib/Target/SparcV8:
SparcV8RegisterInfo.cpp updated: 1.33 -> 1.34
SparcV8RegisterInfo.h updated: 1.6 -> 1.7
---
Log message:
Teach sparc to fold loads/stores into copies.
Remove the dead getRegClassForType method
minor formating changes.
---
Diffs of the changes: (+
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.252 -> 1.253
---
Log message:
remove dead fn
---
Diffs of the changes: (+0 -11)
SelectionDAG.cpp | 11 ---
1 files changed, 11 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.93 -> 1.94
---
Log message:
Add common code for reassociating ops in the dag combiner
---
Diffs of the changes: (+55 -50)
DAGCombiner.cpp | 105 +---
1 files
Changes in directory llvm/test/Regression/CodeGen/X86:
store_op_load_fold.ll added (r1.1)
---
Log message:
Added a (store (op (load ...) ...) ...) folding test case.
---
Diffs of the changes: (+14 -0)
store_op_load_fold.ll | 14 ++
1 files changed, 14 insertions(+)
Index: l
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.cpp updated: 1.9 -> 1.10
SparcV8InstrInfo.h updated: 1.5 -> 1.6
---
Log message:
Implement isLoadFromStackSlot and isStoreToStackSlot
---
Diffs of the changes: (+52 -0)
SparcV8InstrInfo.cpp | 38 ++
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.159 -> 1.160
---
Log message:
(store (op (load ...))) folding problem. In the generated matching code,
Chain is initially set to the chain operand of store node, when it reaches
load, if it matches the load then Chain is se
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.58 -> 1.59
---
Log message:
remove some target-indep and implemented notes
---
Diffs of the changes: (+11 -13)
README.txt | 24 +++-
1 files changed, 11 insertions(+), 13 deletions(-)
Index: llvm/li
Changes in directory llvm/lib/Target:
README.txt added (r1.1)
---
Log message:
target independent notes
---
Diffs of the changes: (+67 -0)
README.txt | 67 +
1 files changed, 67 insertions(+)
Index: llvm/lib/Target/README.txt
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.45 -> 1.46
---
Log message:
remove some target-indep and implemented notes
---
Diffs of the changes: (+0 -44)
README.txt | 44
1 files changed, 44 deletions(-)
Index: llvm/lib/T
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.57 -> 1.58
---
Log message:
Flesh out a couple of the items in the README
---
Diffs of the changes: (+41 -14)
README.txt | 55 +--
1 files changed, 41 insertions(+), 14
Changes in directory llvm/lib/CodeGen:
VirtRegMap.cpp updated: 1.50 -> 1.51
---
Log message:
Fix VC++ compilation error caused by using a std::map iterator variable to
receive
a std::multimap iterator value. For some reason, GCC doesn't have a problem
with this.
---
Diffs of the changes:
Changes in directory llvm/lib/CodeGen:
VirtRegMap.cpp updated: 1.49 -> 1.50
---
Log message:
Remove move copies and dead stuff by not clobbering the result reg of a noop
copy.
---
Diffs of the changes: (+21 -12)
VirtRegMap.cpp | 33 +
1 files changed, 21
Changes in directory llvm/lib/Target/Alpha:
AlphaInstrInfo.cpp updated: 1.7 -> 1.8
AlphaInstrInfo.h updated: 1.4 -> 1.5
AlphaInstrInfo.td updated: 1.112 -> 1.113
---
Log message:
isStoreToStackSlot
---
Diffs of the changes: (+20 -3)
AlphaInstrInfo.cpp | 18 ++
AlphaInstrIn
Changes in directory llvm/lib/CodeGen:
VirtRegMap.cpp updated: 1.48 -> 1.49
---
Log message:
Simplify some code
---
Diffs of the changes: (+40 -45)
VirtRegMap.cpp | 85 ++---
1 files changed, 40 insertions(+), 45 deletions(-)
Index: l
Changes in directory llvm/lib/Target/X86:
X86PeepholeOpt.cpp updated: 1.41 -> 1.42
---
Log message:
the X86 backend no longer needs to delete its own noop copies
---
Diffs of the changes: (+2 -10)
X86PeepholeOpt.cpp | 12 ++--
1 files changed, 2 insertions(+), 10 deletions(-)
I
Changes in directory llvm/lib/CodeGen:
VirtRegMap.cpp updated: 1.47 -> 1.48
---
Log message:
Add code that checks for noop copies, which triggers when either:
1. a target doesn't know how to fold load/stores into copies, or
2. the spiller rewrites the input to a copy to the same register as the
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.56 -> 1.57
---
Log message:
Add a note
---
Diffs of the changes: (+5 -0)
README.txt |5 +
1 files changed, 5 insertions(+)
Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.56
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.251 -> 1.252
---
Log message:
Added case HANDLENODE to getOperationName().
---
Diffs of the changes: (+1 -0)
SelectionDAG.cpp |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/CodeGen/SelectionDAG/Sel
Changes in directory llvm/lib/CodeGen:
VirtRegMap.cpp updated: 1.46 -> 1.47
---
Log message:
Physregs may hold multiple stack slot values at the same time. Keep track
of this, and use it to our advantage (bwahahah). This allows us to eliminate
another
60 instructions from smg2000 on PPC (pro
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.55 -> 1.56
---
Log message:
update a note
---
Diffs of the changes: (+3 -0)
README.txt |3 +++
1 files changed, 3 insertions(+)
Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.5
Changes in directory llvm/lib/CodeGen:
VirtRegMap.cpp updated: 1.45 -> 1.46
---
Log message:
Fix a deficiency in the spiller that Evan noticed. In particular, consider
this code:
store [stack slot #0], R10
= add R14, [stack slot #0]
The spiller didn't know that the store made the valu
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.cpp updated: 1.15 -> 1.16
---
Log message:
add 64b gpr store to the possible list of isStoreToStackSlot opcodes.
---
Diffs of the changes: (+1 -1)
PPCInstrInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.cpp updated: 1.43 -> 1.44
---
Log message:
fix operand numbers
---
Diffs of the changes: (+4 -4)
X86InstrInfo.cpp |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u l
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.cpp updated: 1.14 -> 1.15
PPCInstrInfo.h updated: 1.10 -> 1.11
---
Log message:
implement isStoreToStackSlot for PPC
---
Diffs of the changes: (+19 -1)
PPCInstrInfo.cpp | 19 ++-
PPCInstrInfo.h |1 +
2 files
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrInfo.cpp updated: 1.13 -> 1.14
PPCInstrInfo.h updated: 1.9 -> 1.10
PPCRegisterInfo.cpp updated: 1.42 -> 1.43
PPCRegisterInfo.h updated: 1.9 -> 1.10
---
Log message:
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far
Changes in directory llvm/lib/Target/Alpha:
AlphaInstrInfo.cpp updated: 1.6 -> 1.7
AlphaInstrInfo.h updated: 1.3 -> 1.4
AlphaRegisterInfo.cpp updated: 1.34 -> 1.35
AlphaRegisterInfo.h updated: 1.8 -> 1.9
---
Log message:
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a f
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.cpp updated: 1.42 -> 1.43
X86InstrInfo.h updated: 1.49 -> 1.50
X86RegisterInfo.cpp updated: 1.119 -> 1.120
X86RegisterInfo.h updated: 1.33 -> 1.34
---
Log message:
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far
Changes in directory llvm/lib/CodeGen:
VirtRegMap.cpp updated: 1.44 -> 1.45
---
Log message:
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far
more logical place. Other methods should also be moved if anyoneis interested.
:)
---
Diffs of the changes: (+3 -2)
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.67 -> 1.68
TargetInstrInfo.h updated: 1.82 -> 1.83
---
Log message:
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,
a far more logical place. Other methods should also be moved if anyone
is intere
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.118 -> 1.119
---
Log message:
implement isStoreToStackSlot
---
Diffs of the changes: (+23 -0)
X86RegisterInfo.cpp | 23 +++
1 files changed, 23 insertions(+)
Index: llvm/lib/Target/X86/X86Regis
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.h updated: 1.32 -> 1.33
---
Log message:
add a method
---
Diffs of the changes: (+1 -0)
X86RegisterInfo.h |1 +
1 files changed, 1 insertion(+)
Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86Regist
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.66 -> 1.67
---
Log message:
add a new isStoreToStackSlot method
---
Diffs of the changes: (+10 -1)
MRegisterInfo.h | 11 ++-
1 files changed, 10 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/Targe
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.44 -> 1.45
---
Log message:
more notes
---
Diffs of the changes: (+52 -0)
README.txt | 52
1 files changed, 52 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff -
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.43 -> 1.44
---
Log message:
add a note, I have no idea how important this is.
---
Diffs of the changes: (+24 -0)
README.txt | 24
1 files changed, 24 insertions(+)
Index: llvm/lib/Target/X86/README
Changes in directory llvm/lib/Target/SparcV8:
SparcV8InstrInfo.td updated: 1.116 -> 1.117
---
Log message:
%fcc is not an alias for %fcc0
---
Diffs of the changes: (+4 -4)
SparcV8InstrInfo.td |8
1 files changed, 4 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/SparcV8
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