Changes in directory llvm/lib/Target/X86:
X86InstrInfo.cpp updated: 1.42 -> 1.43
X86InstrInfo.h updated: 1.49 -> 1.50
X86RegisterInfo.cpp updated: 1.119 -> 1.120
X86RegisterInfo.h updated: 1.33 -> 1.34
---
Log message:
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far
more logical place. Other methods should also be moved if anyoneis interested.
:)
---
Diffs of the changes: (+53 -55)
X86InstrInfo.cpp | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
X86InstrInfo.h | 10 +++++-----
X86RegisterInfo.cpp | 46 ----------------------------------------------
X86RegisterInfo.h | 4 ----
4 files changed, 53 insertions(+), 55 deletions(-)
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.42
llvm/lib/Target/X86/X86InstrInfo.cpp:1.43
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.42 Wed Feb 1 17:03:16 2006
+++ llvm/lib/Target/X86/X86InstrInfo.cpp Thu Feb 2 14:12:32 2006
@@ -41,6 +41,54 @@
return false;
}
+unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
+ int &FrameIndex) const {
+ switch (MI->getOpcode()) {
+ default: break;
+ case X86::MOV8rm:
+ case X86::MOV16rm:
+ case X86::MOV32rm:
+ case X86::FpLD64m:
+ case X86::MOVSSrm:
+ case X86::MOVSDrm:
+ if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
+ MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
+ MI->getOperand(2).getImmedValue() == 1 &&
+ MI->getOperand(3).getReg() == 0 &&
+ MI->getOperand(4).getImmedValue() == 0) {
+ FrameIndex = MI->getOperand(1).getFrameIndex();
+ return MI->getOperand(0).getReg();
+ }
+ break;
+ }
+ return 0;
+}
+
+unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
+ int &FrameIndex) const {
+ switch (MI->getOpcode()) {
+ default: break;
+ case X86::MOV8mr:
+ case X86::MOV16mr:
+ case X86::MOV32mr:
+ case X86::FpSTP64m:
+ case X86::MOVSSmr:
+ case X86::MOVSDmr:
+ if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
+ MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
+ MI->getOperand(3).getImmedValue() == 1 &&
+ MI->getOperand(4).getReg() == 0 &&
+ MI->getOperand(5).getImmedValue() == 0) {
+ FrameIndex = MI->getOperand(1).getFrameIndex();
+ return MI->getOperand(4).getReg();
+ }
+ break;
+ }
+ return 0;
+}
+
+
+
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
/// may be able to convert a two-address instruction into a true
Index: llvm/lib/Target/X86/X86InstrInfo.h
diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.49
llvm/lib/Target/X86/X86InstrInfo.h:1.50
--- llvm/lib/Target/X86/X86InstrInfo.h:1.49 Wed Feb 1 00:13:50 2006
+++ llvm/lib/Target/X86/X86InstrInfo.h Thu Feb 2 14:12:32 2006
@@ -179,14 +179,14 @@
///
virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
- //
// Return true if the instruction is a register to register move and
// leave the source and dest operands in the passed parameters.
//
- virtual bool isMoveInstr(const MachineInstr& MI,
- unsigned& sourceReg,
- unsigned& destReg) const;
-
+ bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg,
+ unsigned& destReg) const;
+ unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
+ unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
+
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
/// may be able to convert a two-address instruction into a true
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.119
llvm/lib/Target/X86/X86RegisterInfo.cpp:1.120
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.119 Thu Feb 2 14:00:41 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Feb 2 14:12:32 2006
@@ -116,52 +116,6 @@
BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg);
}
-unsigned X86RegisterInfo::isLoadFromStackSlot(MachineInstr *MI,
- int &FrameIndex) const {
- switch (MI->getOpcode()) {
- default: break;
- case X86::MOV8rm:
- case X86::MOV16rm:
- case X86::MOV32rm:
- case X86::FpLD64m:
- case X86::MOVSSrm:
- case X86::MOVSDrm:
- if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
- MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
- MI->getOperand(2).getImmedValue() == 1 &&
- MI->getOperand(3).getReg() == 0 &&
- MI->getOperand(4).getImmedValue() == 0) {
- FrameIndex = MI->getOperand(1).getFrameIndex();
- return MI->getOperand(0).getReg();
- }
- break;
- }
- return 0;
-}
-
-unsigned X86RegisterInfo::isStoreToStackSlot(MachineInstr *MI,
- int &FrameIndex) const {
- switch (MI->getOpcode()) {
- default: break;
- case X86::MOV8mr:
- case X86::MOV16mr:
- case X86::MOV32mr:
- case X86::FpSTP64m:
- case X86::MOVSSmr:
- case X86::MOVSDmr:
- if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
- MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
- MI->getOperand(3).getImmedValue() == 1 &&
- MI->getOperand(4).getReg() == 0 &&
- MI->getOperand(5).getImmedValue() == 0) {
- FrameIndex = MI->getOperand(1).getFrameIndex();
- return MI->getOperand(4).getReg();
- }
- break;
- }
- return 0;
-}
-
static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex,
MachineInstr *MI) {
Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.33
llvm/lib/Target/X86/X86RegisterInfo.h:1.34
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.33 Thu Feb 2 13:57:16 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.h Thu Feb 2 14:12:32 2006
@@ -41,10 +41,6 @@
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
- unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
- unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
-
-
/// foldMemoryOperand - If this target supports it, fold a load or store of
/// the specified stack slot into the specified machine instruction for the
/// specified operand. If this is possible, the target should perform the
_______________________________________________
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
