Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.284 -> 1.285
---
Log message:
fix a bug
---
Diffs of the changes: (+1 -2)
LegalizeDAG.cpp |3 +--
1 files changed, 1 insertion(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.74 -> 1.75
---
Log message:
Fix a bug in my elimination of ISD::CALL this morning. PPC now has to
provide the expansion for i64 calls itself
---
Diffs of the changes: (+9 -2)
PPCISelLowering.cpp | 11 +-
Changes in directory llvm/lib/Target/X86:
X86Subtarget.cpp updated: 1.14 -> 1.15
---
Log message:
make this work on non-native hosts
---
Diffs of the changes: (+7 -3)
X86Subtarget.cpp | 10 +++---
1 files changed, 7 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86Subtar
Changes in directory llvm/lib/Target/PowerPC:
PPCSubtarget.cpp updated: 1.16 -> 1.17
README.txt updated: 1.47 -> 1.48
---
Log message:
add a note about how we should implement this FIXME from the legalizer:
// FIXME: revisit this when we have some kind of mechanism by which targets
//
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.282 -> 1.283
---
Log message:
Eliminate the need for ExpandOp to set 'needsanotheriteration', as it already
relegalizes the stuff it returns.
Add the ability to custom expand ADD/SUB, so that targets don't need to d
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.281 -> 1.282
---
Log message:
Instead of making callers of ExpandLibCall legalize the result, make
ExpandLibCall do it itself.
---
Diffs of the changes: (+7 -6)
LegalizeDAG.cpp | 13 +++--
1 files chan
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.280 -> 1.281
---
Log message:
Eliminate the need to do another iteration of the legalizer after inserting
a libcall.
---
Diffs of the changes: (+2 -3)
LegalizeDAG.cpp |5 ++---
1 files changed, 2 insertions(
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.141 -> 1.142
---
Log message:
remove method I just added
---
Diffs of the changes: (+0 -7)
SelectionDAGISel.cpp |7 ---
1 files changed, 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/Selecti
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.40 -> 1.41
---
Log message:
remove this method I just added, now is not the time.
---
Diffs of the changes: (+0 -6)
TargetLowering.h |6 --
1 files changed, 6 deletions(-)
Index: llvm/include/llvm/Target/T
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.140 -> 1.141
---
Log message:
add a new callback
---
Diffs of the changes: (+7 -0)
SelectionDAGISel.cpp |7 +++
1 files changed, 7 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGIS
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.39 -> 1.40
---
Log message:
add a new callback
---
Diffs of the changes: (+12 -5)
TargetLowering.h | 17 -
1 files changed, 12 insertions(+), 5 deletions(-)
Index: llvm/include/llvm/Target/Target
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.38 -> 1.39
---
Log message:
Implement Promote for VAARG, and allow it to be custom promoted for people
who don't want the default behavior (Alpha).
---
Diffs of the changes: (+6 -1)
TargetLowering.h |7 ++-
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.279 -> 1.280
SelectionDAGISel.cpp updated: 1.139 -> 1.140
---
Log message:
Implement Promote for VAARG, and allow it to be custom promoted for people
who don't want the default behavior (Alpha).
---
Diffs of the ch
Changes in directory llvm/lib/Target/IA64:
IA64ISelLowering.cpp updated: 1.30 -> 1.31
---
Log message:
Implement Promote for VAARG, and allow it to be custom promoted for people
who don't want the default behavior (Alpha).
---
Diffs of the changes: (+1 -1)
IA64ISelLowering.cpp |2 +-
1
Changes in directory llvm/lib/Target/Alpha:
AlphaISelLowering.cpp updated: 1.33 -> 1.34
AlphaISelLowering.h updated: 1.13 -> 1.14
---
Log message:
Implement Promote for VAARG, and allow it to be custom promoted for people
who don't want the default behavior (Alpha).
---
Diffs of the changes:
Changes in directory llvm-test/SingleSource/UnitTests:
2005-07-17-INT-To-FP.c updated: 1.5 -> 1.6
---
Log message:
Back out last check-in. Turns out we are bug compatible with gcc. :-)
---
Diffs of the changes: (+1 -1)
2005-07-17-INT-To-FP.c |2 +-
1 files changed, 1 insertion(+), 1 del
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.46 -> 1.47
---
Log message:
Add a couple more things to the readme.
---
Diffs of the changes: (+53 -0)
README.txt | 53 +
1 files changed, 53 insertions(+)
Index: llv
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.86 -> 1.87
---
Log message:
Add a missing case to the dag combiner.
---
Diffs of the changes: (+3 -2)
DAGCombiner.cpp |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/Sele
Changes in directory llvm-test/SingleSource/UnitTests:
2005-07-17-INT-To-FP.c updated: 1.4 -> 1.5
---
Log message:
Work around a GCC bug where it is incorrectly eliding a float truncate by
using a value that is fully precise as a float.CVS:
-
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.278 -> 1.279
SelectionDAG.cpp updated: 1.245 -> 1.246
---
Log message:
Remove the ISD::CALL and ISD::TAILCALL nodes
---
Diffs of the changes: (+1 -83)
LegalizeDAG.cpp | 80
Changes in directory llvm/include/llvm/CodeGen:
SelectionDAG.h updated: 1.88 -> 1.89
SelectionDAGNodes.h updated: 1.95 -> 1.96
---
Log message:
The 'target-independent' ISD::CALL isn't. Nuke it, making way for Nate's
future work.
---
Diffs of the changes: (+0 -43)
SelectionDAG.h |
Changes in directory llvm/lib/Target/IA64:
IA64ISelDAGToDAG.cpp updated: 1.30 -> 1.31
IA64ISelLowering.cpp updated: 1.29 -> 1.30
---
Log message:
Remove some dead code
---
Diffs of the changes: (+0 -35)
IA64ISelDAGToDAG.cpp | 30 --
IA64ISelLowering.cpp |5
Changes in directory llvm/lib/Target/Alpha:
AlphaISelDAGToDAG.cpp updated: 1.29 -> 1.30
AlphaISelLowering.cpp updated: 1.32 -> 1.33
AlphaISelLowering.h updated: 1.12 -> 1.13
---
Log message:
Switch to AlphaISD::CALL instead of ISD::CALL
---
Diffs of the changes: (+10 -4)
AlphaISelDAGToDAG.
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.152 -> 1.153
PPCISelLowering.cpp updated: 1.73 -> 1.74
PPCISelLowering.h updated: 1.17 -> 1.18
---
Log message:
Use PPCISD::CALL instead of ISD::CALL
---
Diffs of the changes: (+11 -6)
PPCISelDAGToDAG.cpp |3 +
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.61 -> 1.62
SparcV8InstrInfo.td updated: 1.104 -> 1.105
---
Log message:
Use V8ISD::CALL instead of ISD::CALL
---
Diffs of the changes: (+9 -5)
SparcV8ISelDAGToDAG.cpp | 12
SparcV8InstrInfo.td
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.24 -> 1.25
---
Log message:
A bit of wisdom from Chris on the last entry.
---
Diffs of the changes: (+10 -1)
README.txt | 11 ++-
1 files changed, 10 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/README.t
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.220 -> 1.221
---
Log message:
AT&T assembly convention: registers are in lower case.
---
Diffs of the changes: (+16 -16)
X86InstrInfo.td | 32
1 files changed, 16 insertions(+), 16 delet
Changes in directory llvm/test/Regression/CodeGen/X86:
fp_constant_op.llx updated: 1.1 -> 1.2
fp_load_fold.llx updated: 1.1 -> 1.2
---
Log message:
Use Intel assembly syntax to look for ST
---
Diffs of the changes: (+2 -2)
fp_constant_op.llx |2 +-
fp_load_fold.llx |2 +-
2 files
Changes in directory llvm/lib/Target/SparcV8:
SparcV8Subtarget.cpp updated: 1.2 -> 1.3
---
Log message:
initialize member vars
---
Diffs of the changes: (+5 -0)
SparcV8Subtarget.cpp |5 +
1 files changed, 5 insertions(+)
Index: llvm/lib/Target/SparcV8/SparcV8Subtarget.cpp
diff -u
Changes in directory llvm/lib/Target/X86:
X86Subtarget.cpp updated: 1.13 -> 1.14
---
Log message:
initialize all instance vars
---
Diffs of the changes: (+7 -3)
X86Subtarget.cpp | 10 +++---
1 files changed, 7 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/X86/X86Subtarget.cp
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.146 -> 1.147
DAGISelEmitter.h updated: 1.51 -> 1.52
---
Log message:
Teach tablegen to generate code that is VC++ warning-free.
---
Diffs of the changes: (+65 -23)
DAGISelEmitter.cpp | 86 +
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.72 -> 1.73
PPCISelLowering.h updated: 1.16 -> 1.17
---
Log message:
Make llvm.frame/returnaddr not crash on ppc
---
Diffs of the changes: (+0 -11)
PPCISelLowering.cpp |7 ---
PPCISelLowering.h |4 ---
Changes in directory llvm:
Makefile.rules updated: 1.338 -> 1.339
---
Log message:
* Eliminate FAKE_SOURCES
* Make runtimes and projects build with the new front-end by not relying on
'llvm-gcc -c' to build a .bc file. Instead, use llvm-gcc -S -emit-llvm,
then an explicit invocation of gc
Changes in directory llvm/utils/TableGen:
DAGISelEmitter.cpp updated: 1.145 -> 1.146
---
Log message:
(store (op (load ...)), ...)
If store's chain operand is load, then use load's chain operand instead. If
it isn't (likely a TokenFactor), then do not allow the folding.
---
Diffs of the chang
Changes in directory llvm/lib/Target/X86:
README.txt updated: 1.23 -> 1.24
---
Log message:
Added notes about a x86 isel deficiency.
---
Diffs of the changes: (+22 -0)
README.txt | 22 ++
1 files changed, 22 insertions(+)
Index: llvm/lib/Target/X86/README.txt
diff -
Changes in directory llvm/runtime/GCCLibraries/crtend:
Makefile updated: 1.30 -> 1.31
---
Log message:
Remove out of date comment
---
Diffs of the changes: (+0 -7)
Makefile |7 ---
1 files changed, 7 deletions(-)
Index: llvm/runtime/GCCLibraries/crtend/Makefile
diff -u llvm/runti
Changes in directory llvm/docs:
MakefileGuide.html updated: 1.26 -> 1.27
---
Log message:
Remove FAKE_SOURCES
---
Diffs of the changes: (+1 -9)
MakefileGuide.html | 10 +-
1 files changed, 1 insertion(+), 9 deletions(-)
Index: llvm/docs/MakefileGuide.html
diff -u llvm/docs/Make
Changes in directory llvm/runtime/GCCLibraries/crtend:
Makefile updated: 1.29 -> 1.30
---
Log message:
Remove the only use of FAKE_SOURCES
---
Diffs of the changes: (+11 -3)
Makefile | 14 +++---
1 files changed, 11 insertions(+), 3 deletions(-)
Index: llvm/runtime/GCCLibraries
Changes in directory llvm/lib/Target/X86:
X86Subtarget.cpp updated: 1.12 -> 1.13
---
Log message:
Added a temporary option -enable-x86-sse to enable sse support. It is used by
llc-beta.
---
Diffs of the changes: (+11 -2)
X86Subtarget.cpp | 13 +++--
1 files changed, 11 insertions
Changes in directory llvm-test:
Makefile.programs updated: 1.186 -> 1.187
---
Log message:
X86 llc-beta option: -enable-x86-sse
---
Diffs of the changes: (+1 -1)
Makefile.programs |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm-test/Makefile.programs
diff -u llvm-te
Changes in directory llvm/lib/Target/X86:
X86.h updated: 1.41 -> 1.42
X86ISelLowering.cpp updated: 1.60 -> 1.61
X86TargetMachine.cpp updated: 1.99 -> 1.100
---
Log message:
Bye bye Pattern ISel, hello DAG ISel.
---
Diffs of the changes: (+17 -17)
X86.h|2 +-
X86ISelLowe
Changes in directory llvm/test/Regression/CodeGen/X86:
bswap.ll updated: 1.1 -> 1.2
---
Log message:
X86 dag isel is now (soon) the default.
---
Diffs of the changes: (+2 -2)
bswap.ll |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/test/Regression/CodeGen/X86/bs
Changes in directory llvm/test/Regression/CodeGen/X86:
fabs.ll updated: 1.5 -> 1.6
fildll.ll updated: 1.1 -> 1.2
fp-immediate-shorten.ll updated: 1.1 -> 1.2
negatize_zero.ll updated: 1.1 -> 1.2
---
Log message:
These are fp stack test cases.
---
Diffs of the changes: (+4 -4)
fabs.ll
Changes in directory llvm/test/Regression/CodeGen/X86:
2005-12-03-IndirectTailCall.ll updated: 1.1 -> 1.2
fast-cc-tail-call.ll updated: 1.2 -> 1.3
---
Log message:
XFAIL tailcall test cases until it's implemented.
---
Diffs of the changes: (+2 -0)
2005-12-03-IndirectTailCall.ll |1 +
f
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.71 -> 1.72
PPCISelLowering.h updated: 1.15 -> 1.16
---
Log message:
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
the same functionality. This addresses another piece of bug 680:
http://llv
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.138 -> 1.139
---
Log message:
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
the same functionality. This addresses another piece of bug 680:
http://llvm.cs.uiuc.edu/PR680 . Next,
on
Changes in directory llvm/lib/Target/IA64:
IA64ISelLowering.cpp updated: 1.28 -> 1.29
IA64ISelLowering.h updated: 1.6 -> 1.7
---
Log message:
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
the same functionality. This addresses another piece of bug 680:
http://llvm.c
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.59 -> 1.60
X86ISelLowering.h updated: 1.17 -> 1.18
---
Log message:
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
the same functionality. This addresses another piece of bug 680:
http://llvm.cs
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.37 -> 1.38
---
Log message:
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
the same functionality. This addresses another piece of bug 680:
http://llvm.cs.uiuc.edu/PR680 . Next,
on to fixing
Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp updated: 1.60 -> 1.61
---
Log message:
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
the same functionality. This addresses another piece of bug 680:
http://llvm.cs.uiuc.edu/PR680 . Next,
on to f
Changes in directory llvm-test/External/SPEC/CINT95:
Makefile updated: 1.8 -> 1.9
---
Log message:
no idea why this is disabled, it works
---
Diffs of the changes: (+0 -7)
Makefile |7 ---
1 files changed, 7 deletions(-)
Index: llvm-test/External/SPEC/CINT95/Makefile
diff -u llvm-
Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.23 -> 1.24
---
Log message:
Using bit size of integers instead of ambiguous "long" et all.
---
Diffs of the changes: (+62 -62)
DwarfWriter.cpp | 124
1 files changed,
Changes in directory llvm/include/llvm/CodeGen:
DwarfWriter.h updated: 1.21 -> 1.22
---
Log message:
Using bit size of integers instead of ambiguous "long" et all.
---
Diffs of the changes: (+8 -8)
DwarfWriter.h | 16
1 files changed, 8 insertions(+), 8 deletions(-)
In
Changes in directory llvm-test/External/SPEC/CINT95/126.gcc:
Makefile updated: 1.6 -> 1.7
---
Log message:
set some flags to lessen the errors
---
Diffs of the changes: (+6 -1)
Makefile |7 ++-
1 files changed, 6 insertions(+), 1 deletion(-)
Index: llvm-test/External/SPEC/CINT95/1
Changes in directory llvm/lib/Target/X86:
X86Subtarget.cpp updated: 1.11 -> 1.12
---
Log message:
A better workaround
---
Diffs of the changes: (+5 -6)
X86Subtarget.cpp | 11 +--
1 files changed, 5 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86Subtarget.cpp
diff -u
Changes in directory llvm/include/llvm/CodeGen:
DwarfWriter.h updated: 1.20 -> 1.21
---
Log message:
Sorry - really folowing convention.
---
Diffs of the changes: (+1 -0)
DwarfWriter.h |1 +
1 files changed, 1 insertion(+)
Index: llvm/include/llvm/CodeGen/DwarfWriter.h
diff -u llvm/i
Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.22 -> 1.23
---
Log message:
Sorry - really folowing convention.
---
Diffs of the changes: (+1 -1)
DwarfWriter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u ll
Changes in directory llvm/lib/Target/X86:
X86CodeEmitter.cpp updated: 1.84 -> 1.85
---
Log message:
Unbreak the JIT with SSE
---
Diffs of the changes: (+8 -0)
X86CodeEmitter.cpp |8
1 files changed, 8 insertions(+)
Index: llvm/lib/Target/X86/X86CodeEmitter.cpp
diff -u llvm/l
Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.21 -> 1.22
---
Log message:
Following convention.
---
Diffs of the changes: (+1 -1)
DwarfWriter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u llvm/lib/CodeGen
Changes in directory llvm/lib/Target/X86:
X86Subtarget.cpp updated: 1.10 -> 1.11
---
Log message:
force sse/3dnow off until they work. This fixes all the x86 failures last night
---
Diffs of the changes: (+5 -0)
X86Subtarget.cpp |5 +
1 files changed, 5 insertions(+)
Index: llvm
Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.20 -> 1.21
---
Log message:
fix build
---
Diffs of the changes: (+1 -1)
DwarfWriter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/DwarfWriter.cpp
diff -u llvm/lib/CodeGen/DwarfWriter.
Changes in directory llvm/lib/CodeGen:
MachineDebugInfo.cpp updated: 1.8 -> 1.9
---
Log message:
Fix build error that is apparently only a warning with some compilers.
---
Diffs of the changes: (+1 -1)
MachineDebugInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/CodeGen:
MachineDebugInfo.cpp updated: 1.7 -> 1.8
---
Log message:
Forgot the version number.
---
Diffs of the changes: (+1 -1)
MachineDebugInfo.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/MachineDebugInfo.cpp
diff -
Changes in directory llvm/include/llvm/CodeGen:
DwarfWriter.h updated: 1.19 -> 1.20
MachineDebugInfo.h updated: 1.8 -> 1.9
---
Log message:
Improve visibility/correctness of operand indices in "llvm.db" objects.
Handle 64 in DIEs.
---
Diffs of the changes: (+39 -5)
DwarfWriter.h | 1
Changes in directory llvm/lib/CodeGen:
DwarfWriter.cpp updated: 1.19 -> 1.20
MachineDebugInfo.cpp updated: 1.6 -> 1.7
---
Log message:
Improve visibility/correctness of operand indices in "llvm.db" objects.
Handle 64 in DIEs.
---
Diffs of the changes: (+71 -48)
DwarfWriter.cpp | 59
Changes in directory llvm/Xcode/LLVM.xcodeproj:
project.pbxproj updated: 1.18 -> 1.19
---
Log message:
Catch up on some of the file addition/deletions.
---
Diffs of the changes: (+44 -10)
project.pbxproj | 54 --
1 files changed, 44 ins
Changes in directory llvm/lib/Bytecode/Reader:
Reader.cpp updated: 1.187 -> 1.188
Reader.h updated: 1.27 -> 1.28
---
Log message:
Fix auto-upgrade of intrinsics to work properly with both assembly and
bytecode reading. This code is crufty, the result of much hacking to get things
working correc
Changes in directory llvm/lib/VMCore:
AutoUpgrade.cpp updated: 1.7 -> 1.8
---
Log message:
Fix auto-upgrade of intrinsics to work properly with both assembly and
bytecode reading. This code is crufty, the result of much hacking to get things
working correctly. Cleanup patches will follow.
---
Changes in directory llvm/include/llvm/Assembly:
AutoUpgrade.h updated: 1.3 -> 1.4
---
Log message:
Fix auto-upgrade of intrinsics to work properly with both assembly and
bytecode reading. This code is crufty, the result of much hacking to get things
working correctly. Cleanup patches will foll
Changes in directory llvm/test/Regression/Bytecode:
signed-intrinsics.ll added (r1.1)
signed-intrinsics.ll.bc-16 added (r1.1)
---
Log message:
A test case for ensuring that conversion of old-format intrinsics with
signed arguments get auto-upgraded correctly.
---
Diffs of the changes: (+3 -0
Changes in directory llvm/test/Regression/Bytecode:
old-intrinsics.ll updated: 1.4 -> 1.5
---
Log message:
This now passes.
---
Diffs of the changes: (+0 -3)
old-intrinsics.ll |3 ---
1 files changed, 3 deletions(-)
Index: llvm/test/Regression/Bytecode/old-intrinsics.ll
diff -u llvm/
Changes in directory llvm/lib/Target:
Target.td updated: 1.69 -> 1.70
---
Log message:
Subtarget feature can now set any variable to any value
---
Diffs of the changes: (+5 -5)
Target.td | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/Target.td
d
Changes in directory llvm/lib/Target/X86:
X86.h updated: 1.40 -> 1.41
X86.td updated: 1.18 -> 1.19
X86ISelDAGToDAG.cpp updated: 1.36 -> 1.37
X86ISelLowering.cpp updated: 1.58 -> 1.59
X86ISelLowering.h updated: 1.16 -> 1.17
X86ISelPattern.cpp updated: 1.201 -> 1.202
X86InstrInfo.td updated: 1.219
Changes in directory llvm/lib/Target/PowerPC:
PPC.td updated: 1.10 -> 1.11
---
Log message:
Subtarget feature can now set any variable to any value
---
Diffs of the changes: (+5 -5)
PPC.td | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/PowerPC/P
Changes in directory llvm/lib/Target/SparcV8:
SparcV8.td updated: 1.9 -> 1.10
---
Log message:
Subtarget feature can now set any variable to any value
---
Diffs of the changes: (+3 -3)
SparcV8.td |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/SparcV
Changes in directory llvm/lib/Target/Alpha:
Alpha.td updated: 1.7 -> 1.8
---
Log message:
Subtarget feature can now set any variable to any value
---
Diffs of the changes: (+2 -2)
Alpha.td |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/Alpha/Alpha.td
Changes in directory llvm/utils/TableGen:
SubtargetEmitter.cpp updated: 1.16 -> 1.17
---
Log message:
Subtarget feature can now set any variable to any value
---
Diffs of the changes: (+4 -3)
SubtargetEmitter.cpp |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
Index: llvm
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