Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.138 -> 1.139 --- Log message: Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for the same functionality. This addresses another piece of bug 680: http://llvm.cs.uiuc.edu/PR680 . Next, on to fixing Alpha VAARG, which I broke last time. --- Diffs of the changes: (+22 -37) SelectionDAGISel.cpp | 59 +++++++++++++++++++-------------------------------- 1 files changed, 22 insertions(+), 37 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.138 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.139 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.138 Thu Jan 26 16:24:51 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Jan 27 15:09:21 2006 @@ -496,40 +496,30 @@ DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot())); return; } + std::vector<SDOperand> NewValues; + NewValues.push_back(getRoot()); + for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { + SDOperand RetOp = getValue(I.getOperand(i)); + + // If this is an integer return value, we need to promote it ourselves to + // the full width of a register, since LegalizeOp will use ANY_EXTEND rather + // than sign/zero. + if (MVT::isInteger(RetOp.getValueType()) && + RetOp.getValueType() < MVT::i64) { + MVT::ValueType TmpVT; + if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) + TmpVT = TLI.getTypeToTransformTo(MVT::i32); + else + TmpVT = MVT::i32; - SDOperand Op1 = getValue(I.getOperand(0)); - MVT::ValueType TmpVT; - - switch (Op1.getValueType()) { - default: assert(0 && "Unknown value type!"); - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - // If this is a machine where 32-bits is legal or expanded, promote to - // 32-bits, otherwise, promote to 64-bits. - if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote) - TmpVT = TLI.getTypeToTransformTo(MVT::i32); - else - TmpVT = MVT::i32; - - // Extend integer types to result type. - if (I.getOperand(0)->getType()->isSigned()) - Op1 = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, Op1); - else - Op1 = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, Op1); - break; - case MVT::f32: - // If this is a machine where f32 is promoted to f64, do so now. - if (TLI.getTypeAction(MVT::f32) == TargetLowering::Promote) - Op1 = DAG.getNode(ISD::FP_EXTEND, TLI.getTypeToTransformTo(MVT::f32),Op1); - break; - case MVT::i64: - case MVT::f64: - break; // No extension needed! + if (I.getOperand(i)->getType()->isSigned()) + RetOp = DAG.getNode(ISD::SIGN_EXTEND, TmpVT, RetOp); + else + RetOp = DAG.getNode(ISD::ZERO_EXTEND, TmpVT, RetOp); + } + NewValues.push_back(RetOp); } - // Allow targets to lower this further to meet ABI requirements - DAG.setRoot(TLI.LowerReturnTo(getRoot(), Op1, DAG)); + DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, NewValues)); } void SelectionDAGLowering::visitBr(BranchInst &I) { @@ -1249,11 +1239,6 @@ return 0; } -SDOperand TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, - SelectionDAG &DAG) { - return DAG.getNode(ISD::RET, MVT::Other, Chain, Op); -} - void SelectionDAGLowering::visitVAStart(CallInst &I) { DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(), getValue(I.getOperand(1)), _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
