Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.71 -> 1.72 PPCISelLowering.h updated: 1.15 -> 1.16 --- Log message: Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for the same functionality. This addresses another piece of bug 680: http://llvm.cs.uiuc.edu/PR680 . Next, on to fixing Alpha VAARG, which I broke last time. --- Diffs of the changes: (+27 -27) PPCISelLowering.cpp | 51 +++++++++++++++++++++++++++------------------------ PPCISelLowering.h | 3 --- 2 files changed, 27 insertions(+), 27 deletions(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.71 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.72 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.71 Wed Jan 25 12:52:42 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Jan 27 15:09:22 2006 @@ -110,6 +110,9 @@ setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); setOperationAction(ISD::ConstantPool, MVT::i32, Custom); + // RET must be custom lowered, to meet ABI requirements + setOperationAction(ISD::RET , MVT::Other, Custom); + // VASTART needs to be custom lowered to use the VarArgsFrameIndex setOperationAction(ISD::VASTART , MVT::Other, Custom); @@ -440,6 +443,30 @@ return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR, Op.getOperand(1), Op.getOperand(2)); } + case ISD::RET: { + SDOperand Copy; + + switch(Op.getNumOperands()) { + default: + assert(0 && "Do not know how to return this many arguments!"); + abort(); + case 1: + return SDOperand(); // ret void is legal + case 2: { + MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); + unsigned ArgReg = MVT::isInteger(ArgVT) ? PPC::R3 : PPC::F1; + Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), + SDOperand()); + break; + } + case 3: + Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2), + SDOperand()); + Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1)); + break; + } + return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); + } } return SDOperand(); } @@ -835,30 +862,6 @@ return std::make_pair(RetVal, Chain); } -SDOperand PPCTargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, - SelectionDAG &DAG) { - SDOperand Copy; - switch (Op.getValueType()) { - default: assert(0 && "Unknown type to return!"); - case MVT::i32: - Copy = DAG.getCopyToReg(Chain, PPC::R3, Op, SDOperand()); - break; - case MVT::f32: - case MVT::f64: - Copy = DAG.getCopyToReg(Chain, PPC::F1, Op, SDOperand()); - break; - case MVT::i64: - SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, - DAG.getConstant(1, MVT::i32)); - SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, - DAG.getConstant(0, MVT::i32)); - Copy = DAG.getCopyToReg(Chain, PPC::R3, Hi, SDOperand()); - Copy = DAG.getCopyToReg(Copy, PPC::R4, Lo, Copy.getValue(1)); - break; - } - return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); -} - std::pair<SDOperand, SDOperand> PPCTargetLowering:: LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth, SelectionDAG &DAG) { Index: llvm/lib/Target/PowerPC/PPCISelLowering.h diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.15 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.16 --- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.15 Wed Jan 25 12:21:52 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.h Fri Jan 27 15:09:22 2006 @@ -91,9 +91,6 @@ bool isTailCall, SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG); - virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op, - SelectionDAG &DAG); - virtual std::pair<SDOperand, SDOperand> LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, SelectionDAG &DAG); _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
