s-barannikov wrote:
> The call sequence pseudos are generically processed
So are calls, returns, branches etc. That's why we have isCall, isReturn,
isBranch.
> Calls are quite different and there can be many per target
The fact that we can only have one adjcallstack up/down instruction is a
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@@ -1070,8 +1070,8 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
OS << "namespace llvm {\n";
OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
<< " explicit " << ClassName
- << "(const TargetSubtargetInfo &STI, unsigned CFSetupOpcode = ~0u, "
-
s-barannikov wrote:
Can I propose an alternative? Define these instructions with placeholder
operand derived from bodyless `ptr_rc`, and require targets to provide an
override by deriving from the same `ptr_rc` in addition to
RegisterClass/RegClassByHwMode.
Something like:
```
// Target.td
cl
s-barannikov wrote:
> That might work, but that also is more limiting.
I think it is a good thing. All target-independent pseudo instructions should
have the same semantics across all targets, otherwise they become
target-dependent. If a target can override a standard pseudo instruction in any
@@ -918,16 +918,23 @@ def slice;
def encoder;
def decoder;
-/// PointerLikeRegClass - Values that are designed to have pointer width are
-/// derived from this. TableGen treats the register class as having a symbolic
-/// type that it doesn't know, and resolves the actual regc
@@ -918,16 +918,23 @@ def slice;
def encoder;
def decoder;
-/// PointerLikeRegClass - Values that are designed to have pointer width are
-/// derived from this. TableGen treats the register class as having a symbolic
-/// type that it doesn't know, and resolves the actual regc
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https://github.com/llvm/llvm-project/pull/158273
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LGTM
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@@ -46,20 +46,8 @@ unsigned MipsRegisterInfo::getPICCallReg() { return
Mips::T9; }
const TargetRegisterClass *
MipsRegisterInfo::getPointerRegClass(unsigned Kind) const {
- MipsPtrClass PtrClassKind = static_cast(Kind);
-
- switch (PtrClassKind) {
- case MipsPtrClass::Defa
@@ -916,6 +916,30 @@ DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned
RegNo, uint64_t Address,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGP32RegisterClass(MCInst &Inst, unsigned RegNo,
s-barannikov wrote:
Can you add a comment why
@@ -211,6 +211,21 @@ def FeatureUseIndirectJumpsHazard :
SubtargetFeature<"use-indirect-jump-hazard",
def FeatureStrictAlign
: SubtargetFeature<"strict-align", "StrictAlign", "true",
"Disable unaligned load store for r6">;
+//===-
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LGTM
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s-barannikov wrote:
They seem all lowercase to me :man_shrugging:
```
$ grep -E ": (Register)?Operand" llvm/lib/Target/PowerPC/*.td | cut -d ':' -f
2,3
def s16imm64 : Operand {
def u16imm64 : Operand {
def s17imm64 : Operand {
def tocentry : Operand {
def tlsreg : Operand {
def tlsgd : Operand
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https://github.com/s-barannikov approved this pull request.
LGTM
Is there a reason to not implement the renaming suggestion? (Like it would
require renaming methods in C++ files or so or make the naming inconsistent.)
https://github.com/llvm/llvm-project/pull/158777
@@ -868,10 +868,16 @@ def crbitm: Operand {
def PPCRegGxRCNoR0Operand : AsmOperandClass {
let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
}
-def ptr_rc_nor0 : Operand, PointerLikeRegClass<1> {
+
+def ptr_rc_nor0 : RegClassByHwMode<
+ [PPC32, PPC64],
+ [GPRC_N
@@ -902,7 +908,9 @@ def memri34_pcrel : Operand { // memri, imm is a
34-bit value.
def PPCRegGxRCOperand : AsmOperandClass {
let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
}
-def ptr_rc_idx : Operand, PointerLikeRegClass<0> {
+def ptr_rc_idx : Operand,
--
@@ -868,7 +868,11 @@ def crbitm: Operand {
def PPCRegGxRCNoR0Operand : AsmOperandClass {
let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
}
-def ptr_rc_nor0 : Operand, PointerLikeRegClass<1> {
+
+def ptr_rc_nor0 : Operand,
s-barannikov wrote:
S
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@@ -95,10 +95,27 @@ def HasFSMULD : Predicate<"!Subtarget->hasNoFSMULD()">;
// will pick deprecated instructions.
def UseDeprecatedInsts : Predicate<"Subtarget->useV8DeprecatedInsts()">;
+//===--===//
+// HwMo
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@@ -1070,8 +1070,8 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
OS << "namespace llvm {\n";
OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
<< " explicit " << ClassName
- << "(const TargetSubtargetInfo &STI, unsigned CFSetupOpcode = ~0u, "
-
@@ -929,15 +929,15 @@ ARMBaseInstrInfo::describeLoadedValue(const MachineInstr
&MI,
return TargetInstrInfo::describeLoadedValue(MI, Reg);
}
-const MachineInstrBuilder &
-ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
- unsigned Su
@@ -95,10 +95,27 @@ def HasFSMULD : Predicate<"!Subtarget->hasNoFSMULD()">;
// will pick deprecated instructions.
def UseDeprecatedInsts : Predicate<"Subtarget->useV8DeprecatedInsts()">;
+//===--===//
+// HwMo
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@@ -1070,8 +1070,8 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
OS << "namespace llvm {\n";
OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
<< " explicit " << ClassName
- << "(const TargetSubtargetInfo &STI, unsigned CFSetupOpcode = ~0u, "
-
@@ -113,9 +113,12 @@ struct ExtAddrMode {
///
class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
protected:
- TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
- unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
-
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From 32e1a07943e330424c87c405e9021b61af005d73 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
--
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From 4789335841ea689bf447d427a971df6c4ba6325d Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB ins
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From 4789335841ea689bf447d427a971df6c4ba6325d Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB ins
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156363
>From 97585523dab9c7159877bf33d92ffd4c327a26b0 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:27:48 +0300
Subject: [PATCH] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From 7148b34b69d83b64e825e551f7ca9e7c1f792ddf Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From 7148b34b69d83b64e825e551f7ca9e7c1f792ddf Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From e48805779b288d87477d2e7f9c8fcedcf3850511 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z regist
https://github.com/s-barannikov ready_for_review
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>From b06dce15041c3f8bba6af2104a3fc198842ec02c Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Tue, 2 Sep 2025 10:26:16 +0300
Subject: [PATCH] [ARM] Remove most post-decoding instruction adjustments
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From 5f3f11d56935760eeb354cb40a795ce4f36ebca0 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156363
>From d2968852e5e5a25c2b620b4fc54d9f246e4ce8fc Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:27:48 +0300
Subject: [PATCH] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156540
>From b06dce15041c3f8bba6af2104a3fc198842ec02c Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Tue, 2 Sep 2025 10:26:16 +0300
Subject: [PATCH] [ARM] Remove most post-decoding instruction adjustments
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From 5f3f11d56935760eeb354cb40a795ce4f36ebca0 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
https://github.com/s-barannikov updated
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>From d8cf6c5cb741570760b270d3dc60704e0e6f6857 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156363
>From d6f8e4919a1ead2115f9796839c1f5e98665d6bf Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:27:48 +0300
Subject: [PATCH] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156363
>From d6f8e4919a1ead2115f9796839c1f5e98665d6bf Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:27:48 +0300
Subject: [PATCH] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From d19b8cd451544e87424c1954156a1aaeafa9a7b7 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
--
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156363
>From 97585523dab9c7159877bf33d92ffd4c327a26b0 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:27:48 +0300
Subject: [PATCH] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From a233e69f26b660bb800f519b773b96f5f2d7b07e Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB ins
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156359
>From 54a58aba634a49079976dd9733a320b522f483aa Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From d8cf6c5cb741570760b270d3dc60704e0e6f6857 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
@@ -1230,7 +1230,9 @@ let Uses = [R1, R0] in {
let Defs = [R31R30] in
def SPMZPi : F16<0b100101011000, (outs), (ins ZREG:$z), "spm $z+", []>,
- Requires<[HasSPMX]>;
+ Requires<[HasSPMX]> {
+bits<0> z;
s-barannikov wrote
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>From d19b8cd451544e87424c1954156a1aaeafa9a7b7 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
--
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From a233e69f26b660bb800f519b773b96f5f2d7b07e Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB ins
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From e48805779b288d87477d2e7f9c8fcedcf3850511 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z regist
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156363
>From d2968852e5e5a25c2b620b4fc54d9f246e4ce8fc Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:27:48 +0300
Subject: [PATCH] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From ff4fc2343a93ab8f0592d115f839ff7e36fc063e Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z regist
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From f31a7b8ff6fc270b402ee998b8f7286736762b4b Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From f31a7b8ff6fc270b402ee998b8f7286736762b4b Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156540
>From 408cfbc73717240b713f59a393dcc609004dd6ff Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Tue, 2 Sep 2025 10:26:16 +0300
Subject: [PATCH] [ARM] Remove most post-decoding instruction adjustments
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From ff4fc2343a93ab8f0592d115f839ff7e36fc063e Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z regist
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156359
>From 54a58aba634a49079976dd9733a320b522f483aa Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156540
>From 408cfbc73717240b713f59a393dcc609004dd6ff Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Tue, 2 Sep 2025 10:26:16 +0300
Subject: [PATCH] [ARM] Remove most post-decoding instruction adjustments
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From 32e1a07943e330424c87c405e9021b61af005d73 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
--
https://github.com/s-barannikov edited
https://github.com/llvm/llvm-project/pull/156361
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>From f3b4f276760009154caa8140dc5b92651dfbe4db Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:27:48 +0300
Subject: [PATCH] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From d80acf2607cbe3bdc8beedbad108ddba1f174541 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB ins
https://github.com/s-barannikov edited
https://github.com/llvm/llvm-project/pull/156361
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@@ -38,11 +38,7 @@ class Enc_041d7b : OpcodeHexagon {
let Inst{7-1} = Ii{8-2};
bits <4> Rs16;
let Inst{19-16} = Rs16{3-0};
- bits <5> n1;
- let Inst{28-28} = n1{4-4};
- let Inst{24-23} = n1{3-2};
- let Inst{13-13} = n1{1-1};
- let Inst{8-8} = n1{0-0};
---
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From d80acf2607cbe3bdc8beedbad108ddba1f174541 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB ins
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From 1346d77cc53c6a4152eff9a885244daa360254f7 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z regist
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From d01399ac76d639e7474a8ae382395d1985e64ff7 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
--
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156540
>From a4b01316df9cc4cbaddb92c6f62d3803f5b4600d Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Tue, 2 Sep 2025 10:26:16 +0300
Subject: [PATCH] [ARM] Remove most post-decoding instruction adjustments
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From ee67c361e4f40b314cd8e2ef4b262f5059c2c40d Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From ee67c361e4f40b314cd8e2ef4b262f5059c2c40d Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156363
>From f3b4f276760009154caa8140dc5b92651dfbe4db Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:27:48 +0300
Subject: [PATCH] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156359
>From 01a8d9d7026b94f1cf060a8f12ad27df6e70ee2b Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156540
>From a4b01316df9cc4cbaddb92c6f62d3803f5b4600d Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Tue, 2 Sep 2025 10:26:16 +0300
Subject: [PATCH] [ARM] Remove most post-decoding instruction adjustments
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From d01399ac76d639e7474a8ae382395d1985e64ff7 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
--
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156359
>From 01a8d9d7026b94f1cf060a8f12ad27df6e70ee2b Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From 1346d77cc53c6a4152eff9a885244daa360254f7 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z regist
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From 8b1424a14a78d15c2ecb356cdc4df80a796a0050 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB ins
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156359
>From 26edc73312a06af78a0e3d31f86a2c5bcf97f734 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From 067f93e7a548574db69918a780ec15d060a523a5 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z regist
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156363
>From 772f6554faddeebb5baa7e59e534939f3864c3f8 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:27:48 +0300
Subject: [PATCH] [AArch64] Provide a custom decoder for LDR_ZA/STR_ZA
Th
https://github.com/s-barannikov created
https://github.com/llvm/llvm-project/pull/156360
None
>From cc9f40c359adc78cef0b7350cf9fa42eb045f1ee Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustmen
https://github.com/s-barannikov created
https://github.com/llvm/llvm-project/pull/156361
The generated disassembler can now correctly decode these instructions.
>From a2f114366b405749ebb40fad43bddaf863a05ad5 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
s-barannikov wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/156540?utm_source=stack-comment-downstack-mergeability-warn
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From c66fd0b127a34082ebc277ede621073c121ce0dd Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156359
>From 00683736b4d90916052d2a0635c2e753cc3768e3 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156359
>From b48ce40ecfc85e67b35e7521bf4e185e5471761c Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PATCH] [Hexagon] Remove post-decoding instruction adjustments
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From ed2916521d54928b73305de69b1556d1d8a50f5b Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
https://github.com/s-barannikov created
https://github.com/llvm/llvm-project/pull/156359
These instructions can now be fully decoded automatically.
>From eb4a0870f4a96eddc73d3ae4aaa9dd987c06b832 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:16:14 +0300
Subject: [PAT
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From 9f30122b180122b518a4dca079145846bb87e428 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
--
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From b1cd999acbb29fc53f9eb33284a3e5d2bc72bb11 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z regist
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156360
>From 4188fa46342e6747f985d232677f6a690fa9972c Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:06 +0300
Subject: [PATCH] [RISCV] Remove post-decoding instruction adjustments
--
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156361
>From 235b15d6a19c5810cdbbb2d111b5f614a86082a0 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:18:57 +0300
Subject: [PATCH] [AVR] Remove workarounds for instructions using Z regist
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156364
>From a112090864e21acab35b4a3d71cebe45ae0f22aa Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:30:01 +0300
Subject: [PATCH] [AArch64] Remove post-decoding instruction mutations
Th
https://github.com/s-barannikov updated
https://github.com/llvm/llvm-project/pull/156362
>From c82858d3ba2267af6638e29d2601715b582a2968 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov
Date: Mon, 1 Sep 2025 20:22:53 +0300
Subject: [PATCH] [AArch64] Correctly disassemble TSB instruction
TSB ins
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