s-barannikov wrote:
They seem all lowercase to me :man_shrugging:
```
$ grep -E ": (Register)?Operand" llvm/lib/Target/PowerPC/*.td | cut -d ':' -f
2,3
def s16imm64 : Operand<i64> {
def u16imm64 : Operand<i64> {
def s17imm64 : Operand<i64> {
def tocentry : Operand<iPTR> {
def tlsreg : Operand<i64> {
def tlsgd : Operand<i64> {}
def tlscall : Operand<i64> {
def tocentry32 : Operand<iPTR> {
def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
def gprc : RegisterOperand<GPRC> {
def g8rc : RegisterOperand<G8RC> {
def g8prc : RegisterOperand<G8pRC> {
def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
def f8rc : RegisterOperand<F8RC> {
def f4rc : RegisterOperand<F4RC> {
def fpairrc : RegisterOperand<FpRC> {
def vrrc : RegisterOperand<VRRC> {
def vfrc : RegisterOperand<VFRC> {
def crbitrc : RegisterOperand<CRBITRC> {
def crrc : RegisterOperand<CRRC> {
def sperc : RegisterOperand<SPERC> {
def spe4rc : RegisterOperand<GPRC> {
def u1imm : Operand<i32> {
def u2imm : Operand<i32> {
def atimm : Operand<i32> {
def u3imm : Operand<i32> {
def u4imm : Operand<i32> {
def s5imm : Operand<i32> {
def u5imm : Operand<i32> {
def u6imm : Operand<i32> {
def u7imm : Operand<i32> {
def u8imm : Operand<i32> {
def u10imm : Operand<i32> {
def u12imm : Operand<i32> {
def s16imm : Operand<i32> {
def u16imm : Operand<i32> {
def s17imm : Operand<i32> {
def s34imm : Operand<i64> {
def s34imm_pcrel : Operand<i64> {
def immZero : Operand<i32> {
def directbrtarget : Operand<OtherVT> {
def absdirectbrtarget : Operand<OtherVT> {
def condbrtarget : Operand<OtherVT> {
def abscondbrtarget : Operand<OtherVT> {
def calltarget : Operand<iPTR> {
def abscalltarget : Operand<iPTR> {
def crbitm: Operand<i8> {
def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
def dispRI34 : Operand<iPTR> {
def dispRI34_pcrel : Operand<iPTR> {
def memri34 : Operand<iPTR> { // memri, imm is a 34-bit value.
def memri34_pcrel : Operand<iPTR> { // memri, imm is a 34-bit value.
def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
def dispRI : Operand<iPTR> {
def dispRIX : Operand<iPTR> {
def dispRIHash : Operand<iPTR> {
def dispRIX16 : Operand<iPTR> {
def dispSPE8 : Operand<iPTR> {
def dispSPE4 : Operand<iPTR> {
def dispSPE2 : Operand<iPTR> {
def memri : Operand<iPTR> {
def memrr : Operand<iPTR> {
def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
def memrihash : Operand<iPTR> {
def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16
def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.
def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned.
def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned.
def memr : Operand<iPTR> {
def tlsreg32 : Operand<i32> {
def tlsgd32 : Operand<i32> {}
def tlscall32 : Operand<i32> {
def pred : Operand<OtherVT> {
def vsrc : RegisterOperand<VSRC> {
def vsfrc : RegisterOperand<VSFRC> {
def vssrc : RegisterOperand<VSSRC> {
def spilltovsrrc : RegisterOperand<SPILLTOVSRRC> {
def vsrprc : RegisterOperand<VSRpRC> {
def vsrpevenrc : RegisterOperand<VSRpRC> {
def acc : RegisterOperand<ACCRC> {
def uacc : RegisterOperand<UACCRC> {
def dmrrow : RegisterOperand<DMRROWRC> {
def dmrrowp : RegisterOperand<DMRROWpRC> {
def wacc : RegisterOperand<WACCRC> {
def wacc_hi : RegisterOperand<WACC_HIRC> {
def dmr : RegisterOperand<DMRRC> {
def dmrp : RegisterOperand<DMRpRC> {
```
https://github.com/llvm/llvm-project/pull/158777
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