s-barannikov wrote:
Can I propose an alternative? Define these instructions with placeholder
operand derived from bodyless `ptr_rc`, and require targets to provide an
override by deriving from the same `ptr_rc` in addition to
RegisterClass/RegClassByHwMode.
Something like:
```
// Target.td
class ptr_rc;
def placeholder_ptr_rc : ptr_rc;
def LOAD_STACK_GUARD : StandardPseudoInstruction {
let OutOperandList = (outs placeholder_ptr_rc:$dst);
...
}
// X86InstrOperands.td
def x86_ptr_rc : ptr_rc, RegClassByHwMode<...>;
```
TableGen will replace `placeholder_ptr_rd` with the target-specific subclass of
`ptr_rc` where necessary (checking that there is exactly one override). I can
see an advantage that we can support different address spaces by just adding a
template parameter.
https://github.com/llvm/llvm-project/pull/159880
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