[llvm-branch-commits] [llvm] [Coalescer] Consider NewMI's subreg index when updating lanemask. (PR #121780)

2025-01-06 Thread Sander de Smalen via llvm-branch-commits
https://github.com/sdesmalen-arm created https://github.com/llvm/llvm-project/pull/121780 The code added in #116191 that updated the lanemasks for rematerialized values checked if `DefMI`'s destination register had a subreg index. This seems to have missed the following case: ``` %0:gpr32 = M

[llvm-branch-commits] [llvm] Cherry pick f314e12 into release/19.x (PR #117695)

2024-12-02 Thread Sander de Smalen via llvm-branch-commits
sdesmalen-arm wrote: > Hi! How important are these backports for the release branch? Are they > bugfixes? What's the risk of them? Hi @tru, these are all bugfixes for things that would somehow lead to a compilation failure when targeting AArch64 SME instructions. I don't see any risks in cher

[llvm-branch-commits] [llvm] Cherry pick f314e12 into release/19.x (PR #117695)

2024-11-26 Thread Sander de Smalen via llvm-branch-commits
https://github.com/sdesmalen-arm edited https://github.com/llvm/llvm-project/pull/117695 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] Cherry pick f314e12 into release/19.x (PR #117695)

2024-11-26 Thread Sander de Smalen via llvm-branch-commits
https://github.com/sdesmalen-arm updated https://github.com/llvm/llvm-project/pull/117695 >From de526e5893e901c350fc9bd6d8013d7d1dbd42c6 Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Tue, 13 Aug 2024 00:39:14 -0700 Subject: [PATCH 1/3] [AArch64][Darwin][SME] Don't try to save VG to the sta

[llvm-branch-commits] [llvm] Cherry pick f314e12 into release/19.x (PR #117695)

2024-11-26 Thread Sander de Smalen via llvm-branch-commits
https://github.com/sdesmalen-arm edited https://github.com/llvm/llvm-project/pull/117695 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] Cherry pick f314e12 into release/19.x (PR #117695)

2024-11-26 Thread Sander de Smalen via llvm-branch-commits
https://github.com/sdesmalen-arm created https://github.com/llvm/llvm-project/pull/117695 f314e12 uses `requiresSaveVG` which was introduced in 334a366ba792, which is also missing from the release/19.x branch. I figured it made sense to cherry-pick that one as well. >From de526e5893e901c350fc9

[llvm-branch-commits] [llvm] Cherry pick f314e12 into release/19.x (PR #117695)

2024-11-26 Thread Sander de Smalen via llvm-branch-commits
https://github.com/sdesmalen-arm milestoned https://github.com/llvm/llvm-project/pull/117695 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AArch64] Define high bits of FPR and GPR registers. (PR #114263)

2024-11-04 Thread Sander de Smalen via llvm-branch-commits
sdesmalen-arm wrote: I think I need to create a new PR for this as Github doesn't allow me to reopen and choose a different branch to merge into. https://github.com/llvm/llvm-project/pull/114263 ___ llvm-branch-commits mailing list llvm-branch-commits

[llvm-branch-commits] [llvm] [AArch64] Define high bits of FPR and GPR registers. (PR #114263)

2024-11-04 Thread Sander de Smalen via llvm-branch-commits
sdesmalen-arm wrote: Trying to reopen.. https://github.com/llvm/llvm-project/pull/114263 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AArch64] Define high bits of FPR and GPR registers. (PR #114263)

2024-11-04 Thread Sander de Smalen via llvm-branch-commits
sdesmalen-arm wrote: It wasn't, but I also didn't realise that I closed it. Could Github have done this automatically after the branch it was based of was deleted? (I was about to push the rebased branch of this PR after merging #114391 and #114392) https://github.com/llvm/llvm-project/pull/11

[llvm-branch-commits] [llvm] [AArch64] Define high bits of FPR and GPR registers. (PR #114263)

2024-11-04 Thread Sander de Smalen via llvm-branch-commits
https://github.com/sdesmalen-arm closed https://github.com/llvm/llvm-project/pull/114263 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [TableGen] Fix calculation of Lanemask for RCs with artificial subregs. (PR #114392)

2024-11-04 Thread Sander de Smalen via llvm-branch-commits
https://github.com/sdesmalen-arm updated https://github.com/llvm/llvm-project/pull/114392 >From 303e1c87e0ea835d5892afaa04c9e72d2d1778f4 Mon Sep 17 00:00:00 2001 From: Sander de Smalen Date: Thu, 31 Oct 2024 09:54:52 + Subject: [PATCH] [TableGen] Fix calculation of Lanemask for RCs with ar

[llvm-branch-commits] [llvm] [AArch64] Define high bits of FPR and GPR registers. (PR #114263)

2024-11-01 Thread Sander de Smalen via llvm-branch-commits
@@ -424,6 +424,58 @@ AArch64RegisterInfo::explainReservedReg(const MachineFunction &MF, return {}; } +static SmallVector ReservedHi = { sdesmalen-arm wrote: I don't think there is a bug; the code for moving an instruction goes through the list of operands

[llvm-branch-commits] [llvm] [AArch64] Define high bits of FPR and GPR registers. (PR #114263)

2024-10-31 Thread Sander de Smalen via llvm-branch-commits
@@ -424,6 +424,58 @@ AArch64RegisterInfo::explainReservedReg(const MachineFunction &MF, return {}; } +static SmallVector ReservedHi = { sdesmalen-arm wrote: Without marking the registers as reserved, then for the example below: ``` --- name:sv2

[llvm-branch-commits] [llvm] [AArch64] Define high bits of FPR and GPR registers. (PR #114263)

2024-10-31 Thread Sander de Smalen via llvm-branch-commits
https://github.com/sdesmalen-arm edited https://github.com/llvm/llvm-project/pull/114263 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AArch64] Disable SVE paired ld1/st1 for callee-saves. (PR #107406)

2024-09-10 Thread Sander de Smalen via llvm-branch-commits
sdesmalen-arm wrote: > Hi, since we are wrapping up LLVM 19.1.0 we are very strict with the fixes we > pick at this point. Can you please respond to the following questions to help > me understand if this has to be included in the final release or not. Sure, I appreciate your diligence! > Is

[llvm-branch-commits] [llvm] [AArch64] Disable SVE paired ld1/st1 for callee-saves. (PR #107406)

2024-09-05 Thread Sander de Smalen via llvm-branch-commits
https://github.com/sdesmalen-arm edited https://github.com/llvm/llvm-project/pull/107406 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AArch64] Disable SVE paired ld1/st1 for callee-saves. (PR #107406)

2024-09-05 Thread Sander de Smalen via llvm-branch-commits
https://github.com/sdesmalen-arm milestoned https://github.com/llvm/llvm-project/pull/107406 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] release/19.x: [clang][AArch64] Add SME2.1 feature macros (#105657) (PR #106135)

2024-08-26 Thread Sander de Smalen via llvm-branch-commits
https://github.com/sdesmalen-arm approved this pull request. https://github.com/llvm/llvm-project/pull/106135 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] release/19.x: [clang][AArch64] Add SME2.1 feature macros (#105657) (PR #106135)

2024-08-26 Thread Sander de Smalen via llvm-branch-commits
sdesmalen-arm wrote: Rationale; this helps people who use LLVM 19 to write code for the SME2.1 intrinsics, which the compiler already supports, but without the macros set a user couldn't write compliant code, e.g. `#if defined __ARM_FEATURE_SME_B16B16, , #endif`, because the macro would not be

[llvm-branch-commits] [clang] [llvm] [AArch64] Adopt updated B16B16 target flags (PR #104602)

2024-08-16 Thread Sander de Smalen via llvm-branch-commits
https://github.com/sdesmalen-arm approved this pull request. Thanks for making this change! The Clang/driver behaviour looks correct to me now. The patch is a lot smaller than the patches that went into main, so hopefully this can still make it into LLVM 19! https://github.com/llvm/llvm-projec

[llvm-branch-commits] [llvm] release/19.x: [LLVM][TTI][SME] Allow optional auto-vectorisation for streaming functions. (#101679) (PR #101959)

2024-08-05 Thread Sander de Smalen via llvm-branch-commits
https://github.com/sdesmalen-arm approved this pull request. https://github.com/llvm/llvm-project/pull/101959 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] release/19.x: Reland: "[Clang] Demote always_inline error to warning for mismatching SME attrs" (#100991) (#100996) (PR #101303)

2024-08-01 Thread Sander de Smalen via llvm-branch-commits
sdesmalen-arm wrote: > Is this safe enough to reland? Have it lived without a problem in main for a > bit? Thanks for checking. The only failures I would have expected are from lit tests, but the PR was merged on Monday and I've not seen any buildbot failures, so I believe it is safe. There

[llvm-branch-commits] [clang] [clang][FMV][AArch64] Improve streaming mode compatibility (PR #101007)

2024-07-31 Thread Sander de Smalen via llvm-branch-commits
https://github.com/sdesmalen-arm approved this pull request. It would be good if this could make it into the LLVM 19 release. https://github.com/llvm/llvm-project/pull/101007 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https

[llvm-branch-commits] [clang] release/19.x: [Clang] Demote always_inline error to warning for mismatching SME attrs (#100740) (PR #100987)

2024-07-29 Thread Sander de Smalen via llvm-branch-commits
https://github.com/sdesmalen-arm requested changes to this pull request. For some odd reason, `clang/test/CodeGen/aarch64-sme-inline-streaming-attrs.c` seems to be failing on some buildbots with an error that says: > `unable to create target: No available targets are compatible with triple > "a

[llvm-branch-commits] [compiler-rt] release/19.x: [AArch64][SME] Rewrite __arm_get_current_vg to preserve required registers (#100143) (PR #100546)

2024-07-25 Thread Sander de Smalen via llvm-branch-commits
sdesmalen-arm wrote: It would be great if we could merge this fix into the release branch! https://github.com/llvm/llvm-project/pull/100546 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/l

[llvm-branch-commits] [llvm] [AArch64] Improve cost model for legal subvec insert/extract (PR #81135)

2024-02-15 Thread Sander de Smalen via llvm-branch-commits
@@ -568,6 +568,48 @@ AArch64TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, } return Cost; } + case Intrinsic::vector_extract: { +// If both the vector argument and the return type are legal types and the +// index is 0, then this should b

[llvm-branch-commits] [llvm] [AArch64] Improve cost model for legal subvec insert/extract (PR #81135)

2024-02-15 Thread Sander de Smalen via llvm-branch-commits
@@ -568,6 +568,48 @@ AArch64TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, } return Cost; } + case Intrinsic::vector_extract: { +// If both the vector argument and the return type are legal types and the +// index is 0, then this should b

[llvm-branch-commits] [llvm] [AArch64] Improve cost model for legal subvec insert/extract (PR #81135)

2024-02-15 Thread Sander de Smalen via llvm-branch-commits
@@ -568,6 +568,32 @@ AArch64TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, } return Cost; } + case Intrinsic::vector_extract: { +// If both the vector argument and the return type are legal types, then +// this should be a no-op or simple

[llvm-branch-commits] [clang] [llvm] release/18.x: [AArch64][SME] Implement inline-asm clobbers for za/zt0 (#79276) (PR #81616)

2024-02-14 Thread Sander de Smalen via llvm-branch-commits
https://github.com/sdesmalen-arm approved this pull request. Looks pretty low-risk to me and would be nice to get into the release if we can. (how is this PR different from #81593?) https://github.com/llvm/llvm-project/pull/81616 ___ llvm-branch-commi

[llvm-branch-commits] [clang] [llvm] release/18.x: [AArch64][SME] Implement inline-asm clobbers for za/zt0 (#79276) (PR #81593)

2024-02-13 Thread Sander de Smalen via llvm-branch-commits
https://github.com/sdesmalen-arm approved this pull request. Looks pretty low-risk to me and would be nice to get into the release if we can. https://github.com/llvm/llvm-project/pull/81593 ___ llvm-branch-commits mailing list llvm-branch-commits@lists

[llvm-branch-commits] [llvm] 329fda3 - NFC: Mention auto-vec support for SVE in release notes.

2022-03-15 Thread Sander de Smalen via llvm-branch-commits
Author: Sander de Smalen Date: 2022-03-14T09:44:55Z New Revision: 329fda39c507e8740978d10458451dcdb21563be URL: https://github.com/llvm/llvm-project/commit/329fda39c507e8740978d10458451dcdb21563be DIFF: https://github.com/llvm/llvm-project/commit/329fda39c507e8740978d10458451dcdb21563be.diff L

[llvm-branch-commits] [llvm] 171d124 - [SLPVectorizer] NFC: Migrate getVectorCallCosts to use InstructionCost.

2021-01-25 Thread Sander de Smalen via llvm-branch-commits
Author: Sander de Smalen Date: 2021-01-25T12:27:01Z New Revision: 171d12489f20818e292362342b5665c689073ad2 URL: https://github.com/llvm/llvm-project/commit/171d12489f20818e292362342b5665c689073ad2 DIFF: https://github.com/llvm/llvm-project/commit/171d12489f20818e292362342b5665c689073ad2.diff L

[llvm-branch-commits] [llvm] d196f9e - [InstructionCost] Prevent InstructionCost being created with CostState.

2021-01-25 Thread Sander de Smalen via llvm-branch-commits
Author: Sander de Smalen Date: 2021-01-25T11:26:56Z New Revision: d196f9e2fca3ff767aa7d2dcaf4654724a79e18c URL: https://github.com/llvm/llvm-project/commit/d196f9e2fca3ff767aa7d2dcaf4654724a79e18c DIFF: https://github.com/llvm/llvm-project/commit/d196f9e2fca3ff767aa7d2dcaf4654724a79e18c.diff L

[llvm-branch-commits] [llvm] c8a914d - [LiveDebugValues] Fix comparison operator in VarLocBasedImpl

2021-01-12 Thread Sander de Smalen via llvm-branch-commits
Author: Sander de Smalen Date: 2021-01-12T08:44:58Z New Revision: c8a914db5c60dbeb5b638f30a9915855a67805f7 URL: https://github.com/llvm/llvm-project/commit/c8a914db5c60dbeb5b638f30a9915855a67805f7 DIFF: https://github.com/llvm/llvm-project/commit/c8a914db5c60dbeb5b638f30a9915855a67805f7.diff L

[llvm-branch-commits] [llvm] aa280c9 - [AArch64][SVE] Emit DWARF location expr for SVE (dbg.declare)

2021-01-06 Thread Sander de Smalen via llvm-branch-commits
Author: Sander de Smalen Date: 2021-01-06T11:45:05Z New Revision: aa280c99f708dca9dea96bc9070d6194d2622529 URL: https://github.com/llvm/llvm-project/commit/aa280c99f708dca9dea96bc9070d6194d2622529 DIFF: https://github.com/llvm/llvm-project/commit/aa280c99f708dca9dea96bc9070d6194d2622529.diff L

[llvm-branch-commits] [llvm] 84a1120 - [LiveDebugValues] Handle spill locations with a fixed and scalable component.

2021-01-06 Thread Sander de Smalen via llvm-branch-commits
Author: Sander de Smalen Date: 2021-01-06T11:30:13Z New Revision: 84a1120943a651184bae507fed5d648fee381ae4 URL: https://github.com/llvm/llvm-project/commit/84a1120943a651184bae507fed5d648fee381ae4 DIFF: https://github.com/llvm/llvm-project/commit/84a1120943a651184bae507fed5d648fee381ae4.diff L

[llvm-branch-commits] [llvm] e4cda13 - Fix test failure in a7e3339f3b0eb71e43d44e6f59cc8db6a7b110bf

2021-01-06 Thread Sander de Smalen via llvm-branch-commits
Author: Sander de Smalen Date: 2021-01-06T10:43:48Z New Revision: e4cda13d5a54a8c6366e4ca82d74265e68bbb3f5 URL: https://github.com/llvm/llvm-project/commit/e4cda13d5a54a8c6366e4ca82d74265e68bbb3f5 DIFF: https://github.com/llvm/llvm-project/commit/e4cda13d5a54a8c6366e4ca82d74265e68bbb3f5.diff L

[llvm-branch-commits] [llvm] a7e3339 - [AArch64][SVE] Emit DWARF location expression for SVE stack objects.

2021-01-06 Thread Sander de Smalen via llvm-branch-commits
Author: Sander de Smalen Date: 2021-01-06T09:40:53Z New Revision: a7e3339f3b0eb71e43d44e6f59cc8db6a7b110bf URL: https://github.com/llvm/llvm-project/commit/a7e3339f3b0eb71e43d44e6f59cc8db6a7b110bf DIFF: https://github.com/llvm/llvm-project/commit/a7e3339f3b0eb71e43d44e6f59cc8db6a7b110bf.diff L

[llvm-branch-commits] [llvm] a9f5e43 - [AArch64] Use faddp to implement fadd reductions.

2021-01-06 Thread Sander de Smalen via llvm-branch-commits
Author: Sander de Smalen Date: 2021-01-06T09:36:51Z New Revision: a9f5e4375b36e5316b8d6f9731be6bfa5a70e276 URL: https://github.com/llvm/llvm-project/commit/a9f5e4375b36e5316b8d6f9731be6bfa5a70e276 DIFF: https://github.com/llvm/llvm-project/commit/a9f5e4375b36e5316b8d6f9731be6bfa5a70e276.diff L

[llvm-branch-commits] [llvm] d568cff - [LoopVectorizer][SVE] Vectorize a simple loop with with a scalable VF.

2020-12-09 Thread Sander de Smalen via llvm-branch-commits
Author: Sander de Smalen Date: 2020-12-09T11:25:21Z New Revision: d568cff696e8fb89ce1b040561c037412767af60 URL: https://github.com/llvm/llvm-project/commit/d568cff696e8fb89ce1b040561c037412767af60 DIFF: https://github.com/llvm/llvm-project/commit/d568cff696e8fb89ce1b040561c037412767af60.diff L

[llvm-branch-commits] [llvm] adc3714 - [LoopVectorizer] NFC: Remove unnecessary asserts that VF cannot be scalable.

2020-12-09 Thread Sander de Smalen via llvm-branch-commits
Author: Sander de Smalen Date: 2020-12-09T11:25:21Z New Revision: adc37145dec9cadf76af05326150ed22a3cc2fdd URL: https://github.com/llvm/llvm-project/commit/adc37145dec9cadf76af05326150ed22a3cc2fdd DIFF: https://github.com/llvm/llvm-project/commit/adc37145dec9cadf76af05326150ed22a3cc2fdd.diff L