https://github.com/sdesmalen-arm updated https://github.com/llvm/llvm-project/pull/114392
>From 303e1c87e0ea835d5892afaa04c9e72d2d1778f4 Mon Sep 17 00:00:00 2001 From: Sander de Smalen <sander.desma...@arm.com> Date: Thu, 31 Oct 2024 09:54:52 +0000 Subject: [PATCH] [TableGen] Fix calculation of Lanemask for RCs with artificial subregs. TableGen builds up a map of "SubRegIdx -> Subclass" where Subclass is the largest class where all registers have SubRegIdx as a sub-register. When SubRegIdx (vis-a-vis the sub-register) is artificial it should still include it in the map. This map is used in various places, including in the calculation of the Lanemask of a register class, which otherwise calculates an incorrect lanemask. --- llvm/test/TableGen/ArtificialSubregs.td | 4 ++-- llvm/utils/TableGen/Common/CodeGenRegisters.cpp | 10 ++++------ 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/llvm/test/TableGen/ArtificialSubregs.td b/llvm/test/TableGen/ArtificialSubregs.td index dbac129fb2463b..b8d5686dee51be 100644 --- a/llvm/test/TableGen/ArtificialSubregs.td +++ b/llvm/test/TableGen/ArtificialSubregs.td @@ -104,7 +104,7 @@ def TestTarget : Target; // CHECK: SuperClasses: // // CHECK: RegisterClass DRegs: -// CHECK: LaneMask: 0000000000000004 +// CHECK: LaneMask: 0000000000000044 // CHECK: HasDisjunctSubRegs: 1 // CHECK: CoveredBySubRegs: 1 // CHECK: Regs: D0 D1 D2 @@ -112,7 +112,7 @@ def TestTarget : Target; // CHECK: SuperClasses: // // CHECK: RegisterClass QRegs: -// CHECK: LaneMask: 0000000000000044 +// CHECK: LaneMask: 0000000000000045 // CHECK: HasDisjunctSubRegs: 1 // CHECK: CoveredBySubRegs: 1 // CHECK: Regs: Q0 Q1 Q2 diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp index 2bf6a3740c486b..2dbee94d7e5406 100644 --- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp +++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp @@ -2300,10 +2300,8 @@ void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) { if (R->Artificial) continue; const CodeGenRegister::SubRegMap &SRM = R->getSubRegs(); - for (auto I : SRM) { - if (!I.first->Artificial) - SRSets[I.first].push_back(R); - } + for (auto I : SRM) + SRSets[I.first].push_back(R); } for (auto I : SRSets) @@ -2312,8 +2310,6 @@ void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) { // Find matching classes for all SRSets entries. Iterate in SubRegIndex // numerical order to visit synthetic indices last. for (const auto &SubIdx : SubRegIndices) { - if (SubIdx.Artificial) - continue; SubReg2SetMap::const_iterator I = SRSets.find(&SubIdx); // Unsupported SubRegIndex. Skip it. if (I == SRSets.end()) @@ -2323,6 +2319,8 @@ void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) { RC->setSubClassWithSubReg(&SubIdx, RC); continue; } + if (SubIdx.Artificial) + continue; // This is a real subset. See if we have a matching class. CodeGenRegisterClass *SubRC = getOrCreateSubClass( RC, &I->second, RC->getName() + "_with_" + I->first->getName()); _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits