================
@@ -424,6 +424,58 @@ AArch64RegisterInfo::explainReservedReg(const
MachineFunction &MF,
return {};
}
+static SmallVector<MCPhysReg> ReservedHi = {
----------------
sdesmalen-arm wrote:
I don't think there is a bug; the code for moving an instruction goes through
the list of operands to update the register's liverange. For each physreg it
then goes through the regunits to calculate/update the liverange for that
regunit, but only if the regunit is not reserved.
The code that determines if the register is reserved says:
```
// A register unit is considered reserved if all its roots and all their
// super registers are reserved.
```
Without this change to AArch64RegisterInfo.cpp, WZR and XZR are marked as
reserved, but WZR_HI isn't (because WZR_HI is a sibling of WZR, and
`markSuperRegs` marks only XZR as reserved), and so `IsReserved` is `false` for
the WZR_HI regunit.
Why this doesn't fail for AMDGPU I don't know, perhaps these registers are
always virtual and they never go down this path.
https://github.com/llvm/llvm-project/pull/114263
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