[llvm-branch-commits] [llvm] [AMDGPU] Intrinsic for launching whole wave functions (PR #145859)

2025-07-13 Thread Carl Ritson via llvm-branch-commits
https://github.com/perlfu approved this pull request. LGTM But I am unsure if request for tests from @arsenm is fully satisfied. https://github.com/llvm/llvm-project/pull/145859 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org h

[llvm-branch-commits] [llvm] [AMDGPU] Allocate scratch space for dVGPRs for CWSR (PR #130055)

2025-03-11 Thread Carl Ritson via llvm-branch-commits
https://github.com/perlfu approved this pull request. LGTM nit: can you note somewhere (in a comment) that `ScratchReservedForDynamicVGPRs` is in bytes -- the magic divide by 4 to set `dynamic_vgpr_saved_count` was not entirely obvious. https://github.com/llvm/llvm-project/pull/130055 ___

[llvm-branch-commits] [llvm] [AMDGPU] Allocate scratch space for dVGPRs for CWSR (PR #130055)

2025-03-06 Thread Carl Ritson via llvm-branch-commits
@@ -691,17 +691,61 @@ void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF, } assert(ScratchWaveOffsetReg || !PreloadedScratchWaveOffsetReg); - if (hasFP(MF)) { + unsigned Offset = FrameInfo.getStackSize() * getScratchScaleFactor(ST); + if (!mayReserveSc

[llvm-branch-commits] [llvm] [AMDGPU] Allocate scratch space for dVGPRs for CWSR (PR #130055)

2025-03-06 Thread Carl Ritson via llvm-branch-commits
@@ -552,6 +552,7 @@ enum Id { // HwRegCode, (6) [5:0] enum Offset : unsigned { // Offset, (5) [10:6] OFFSET_MEM_VIOL = 8, + OFFSET_ME_ID = 8, perlfu wrote: It's slightly confusing that this enumeration of offsets applies to multiple registers. Perhaps com

[llvm-branch-commits] [llvm] AMDGPU: Replace amdgpu-no-agpr with amdgpu-num-agpr (PR #129893)

2025-03-05 Thread Carl Ritson via llvm-branch-commits
@@ -603,11 +601,7 @@ SIRegisterInfo::getMaxNumVectorRegs(const MachineFunction &MF) const { if (MinNumAGPRs == DefaultNumAGPR.first) { // Default to splitting half the registers if AGPRs are required. - - if (MFI->mayNeedAGPRs()) -MinNumAGPRs = MaxNumAG

[llvm-branch-commits] [llvm] [AMDGPU] Disable VALU sinking and hoisting with WWM (PR #123124)

2025-01-16 Thread Carl Ritson via llvm-branch-commits
perlfu wrote: I guess my concern is performance regressions if any use of WWM (e.g. atomic optimizer) essentially turns off Machine LICM. https://github.com/llvm/llvm-project/pull/123124 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.l

[llvm-branch-commits] [llvm] a80ebd0 - [AMDGPU] Fix llvm.amdgcn.init.exec and frame materialization

2021-01-24 Thread Carl Ritson via llvm-branch-commits
Author: Carl Ritson Date: 2021-01-25T08:31:17+09:00 New Revision: a80ebd01798ca82a4f5ffd6d355c5c9facd83375 URL: https://github.com/llvm/llvm-project/commit/a80ebd01798ca82a4f5ffd6d355c5c9facd83375 DIFF: https://github.com/llvm/llvm-project/commit/a80ebd01798ca82a4f5ffd6d355c5c9facd83375.diff L

[llvm-branch-commits] [llvm] 790c75c - [AMDGPU] Add SI_EARLY_TERMINATE_SCC0 for early terminating shader

2021-01-12 Thread Carl Ritson via llvm-branch-commits
Author: Carl Ritson Date: 2021-01-13T13:29:05+09:00 New Revision: 790c75c16373d37846c8433a69efd9b0d5e4ad12 URL: https://github.com/llvm/llvm-project/commit/790c75c16373d37846c8433a69efd9b0d5e4ad12 DIFF: https://github.com/llvm/llvm-project/commit/790c75c16373d37846c8433a69efd9b0d5e4ad12.diff L

[llvm-branch-commits] [llvm] 7722494 - [AMDGPU][NFC] Remove unused Hi16Elt definition

2020-12-18 Thread Carl Ritson via llvm-branch-commits
Author: Carl Ritson Date: 2020-12-18T20:38:54+09:00 New Revision: 7722494834a8357a42d3da70d22f4a9d87c78e2c URL: https://github.com/llvm/llvm-project/commit/7722494834a8357a42d3da70d22f4a9d87c78e2c DIFF: https://github.com/llvm/llvm-project/commit/7722494834a8357a42d3da70d22f4a9d87c78e2c.diff L

[llvm-branch-commits] [llvm] b58b440 - [AMDGPU][NFC] Document high parameter of f16 interp intrinsics

2020-12-18 Thread Carl Ritson via llvm-branch-commits
Author: Carl Ritson Date: 2020-12-18T19:59:13+09:00 New Revision: b58b440d19c84f59aae4679608c55db0d95ff879 URL: https://github.com/llvm/llvm-project/commit/b58b440d19c84f59aae4679608c55db0d95ff879 DIFF: https://github.com/llvm/llvm-project/commit/b58b440d19c84f59aae4679608c55db0d95ff879.diff L

[llvm-branch-commits] [llvm] 62c246e - [AMDGPU][NFC] Rename opsel/opsel_hi/neg_lo/neg_hi with suffix 0

2020-12-14 Thread Carl Ritson via llvm-branch-commits
Author: Carl Ritson Date: 2020-12-14T20:01:56+09:00 New Revision: 62c246eda24c362f1aa5a71f2cf11f9df5642460 URL: https://github.com/llvm/llvm-project/commit/62c246eda24c362f1aa5a71f2cf11f9df5642460 DIFF: https://github.com/llvm/llvm-project/commit/62c246eda24c362f1aa5a71f2cf11f9df5642460.diff L

[llvm-branch-commits] [llvm] af4570c - [AMDGPU][NFC] Remove unused VOP3Mods0Clamp

2020-12-14 Thread Carl Ritson via llvm-branch-commits
Author: Carl Ritson Date: 2020-12-14T20:00:58+09:00 New Revision: af4570cd3ab94dd52574874b0e9c91a4f6e39272 URL: https://github.com/llvm/llvm-project/commit/af4570cd3ab94dd52574874b0e9c91a4f6e39272 DIFF: https://github.com/llvm/llvm-project/commit/af4570cd3ab94dd52574874b0e9c91a4f6e39272.diff L