================ @@ -603,11 +601,7 @@ SIRegisterInfo::getMaxNumVectorRegs(const MachineFunction &MF) const { if (MinNumAGPRs == DefaultNumAGPR.first) { // Default to splitting half the registers if AGPRs are required. - - if (MFI->mayNeedAGPRs()) - MinNumAGPRs = MaxNumAGPRs = MaxVectorRegs / 2; - else - MinNumAGPRs = 0; ---------------- perlfu wrote:
I guess the removal of the forced minima yields no functional change? https://github.com/llvm/llvm-project/pull/129893 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits