Author: Carl Ritson Date: 2020-12-14T20:01:56+09:00 New Revision: 62c246eda24c362f1aa5a71f2cf11f9df5642460
URL: https://github.com/llvm/llvm-project/commit/62c246eda24c362f1aa5a71f2cf11f9df5642460 DIFF: https://github.com/llvm/llvm-project/commit/62c246eda24c362f1aa5a71f2cf11f9df5642460.diff LOG: [AMDGPU][NFC] Rename opsel/opsel_hi/neg_lo/neg_hi with suffix 0 These parameters set a default value of 0, so I believe they should include a 0 suffix. This allows for versions which do not set a default value in future. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D93187 Added: Modified: llvm/lib/Target/AMDGPU/SIInstrInfo.td llvm/lib/Target/AMDGPU/VOP3Instructions.td llvm/lib/Target/AMDGPU/VOP3PInstructions.td Removed: ################################################################################ diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index 295030d80240..5a6c81a0c89b 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -1136,10 +1136,10 @@ def src0_sel : NamedOperandU32<"SDWASrc0Sel", NamedMatchClass<"SDWASrc0Sel">>; def src1_sel : NamedOperandU32<"SDWASrc1Sel", NamedMatchClass<"SDWASrc1Sel">>; def dst_unused : NamedOperandU32<"SDWADstUnused", NamedMatchClass<"SDWADstUnused">>; -def op_sel : NamedOperandU32Default0<"OpSel", NamedMatchClass<"OpSel">>; -def op_sel_hi : NamedOperandU32Default0<"OpSelHi", NamedMatchClass<"OpSelHi">>; -def neg_lo : NamedOperandU32Default0<"NegLo", NamedMatchClass<"NegLo">>; -def neg_hi : NamedOperandU32Default0<"NegHi", NamedMatchClass<"NegHi">>; +def op_sel0 : NamedOperandU32Default0<"OpSel", NamedMatchClass<"OpSel">>; +def op_sel_hi0 : NamedOperandU32Default0<"OpSelHi", NamedMatchClass<"OpSelHi">>; +def neg_lo0 : NamedOperandU32Default0<"NegLo", NamedMatchClass<"NegLo">>; +def neg_hi0 : NamedOperandU32Default0<"NegHi", NamedMatchClass<"NegHi">>; def blgp : NamedOperandU32<"BLGP", NamedMatchClass<"BLGP">>; def cbsz : NamedOperandU32<"CBSZ", NamedMatchClass<"CBSZ">>; @@ -1677,25 +1677,25 @@ class getInsVOP3P <RegisterOperand Src0RC, RegisterOperand Src1RC, (ins Src0Mod:$src0_modifiers, Src0RC:$src0, Src1Mod:$src1_modifiers, Src1RC:$src1, clampmod0:$clamp, - op_sel:$op_sel, op_sel_hi:$op_sel_hi, - neg_lo:$neg_lo, neg_hi:$neg_hi), + op_sel0:$op_sel, op_sel_hi0:$op_sel_hi, + neg_lo0:$neg_lo, neg_hi0:$neg_hi), (ins Src0Mod:$src0_modifiers, Src0RC:$src0, Src1Mod:$src1_modifiers, Src1RC:$src1, - op_sel:$op_sel, op_sel_hi:$op_sel_hi, - neg_lo:$neg_lo, neg_hi:$neg_hi)), + op_sel0:$op_sel, op_sel_hi0:$op_sel_hi, + neg_lo0:$neg_lo, neg_hi0:$neg_hi)), // else NumSrcArgs == 3 !if (HasClamp, (ins Src0Mod:$src0_modifiers, Src0RC:$src0, Src1Mod:$src1_modifiers, Src1RC:$src1, Src2Mod:$src2_modifiers, Src2RC:$src2, clampmod0:$clamp, - op_sel:$op_sel, op_sel_hi:$op_sel_hi, - neg_lo:$neg_lo, neg_hi:$neg_hi), + op_sel0:$op_sel, op_sel_hi0:$op_sel_hi, + neg_lo0:$neg_lo, neg_hi0:$neg_hi), (ins Src0Mod:$src0_modifiers, Src0RC:$src0, Src1Mod:$src1_modifiers, Src1RC:$src1, Src2Mod:$src2_modifiers, Src2RC:$src2, - op_sel:$op_sel, op_sel_hi:$op_sel_hi, - neg_lo:$neg_lo, neg_hi:$neg_hi)) + op_sel0:$op_sel, op_sel_hi0:$op_sel_hi, + neg_lo0:$neg_lo, neg_hi0:$neg_hi)) ); } @@ -1712,21 +1712,21 @@ class getInsVOP3OpSel <RegisterOperand Src0RC, (ins Src0Mod:$src0_modifiers, Src0RC:$src0, Src1Mod:$src1_modifiers, Src1RC:$src1, clampmod0:$clamp, - op_sel:$op_sel), + op_sel0:$op_sel), (ins Src0Mod:$src0_modifiers, Src0RC:$src0, Src1Mod:$src1_modifiers, Src1RC:$src1, - op_sel:$op_sel)), + op_sel0:$op_sel)), // else NumSrcArgs == 3 !if (HasClamp, (ins Src0Mod:$src0_modifiers, Src0RC:$src0, Src1Mod:$src1_modifiers, Src1RC:$src1, Src2Mod:$src2_modifiers, Src2RC:$src2, clampmod0:$clamp, - op_sel:$op_sel), + op_sel0:$op_sel), (ins Src0Mod:$src0_modifiers, Src0RC:$src0, Src1Mod:$src1_modifiers, Src1RC:$src1, Src2Mod:$src2_modifiers, Src2RC:$src2, - op_sel:$op_sel)) + op_sel0:$op_sel)) ); } diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td index a2ff89fa94d3..28e4a09069a8 100644 --- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td @@ -694,7 +694,7 @@ def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3 let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0, IntOpSelMods:$src1_modifiers, SCSrc_b32:$src1, IntOpSelMods:$src2_modifiers, SCSrc_b32:$src2, - VGPR_32:$vdst_in, op_sel:$op_sel); + VGPR_32:$vdst_in, op_sel0:$op_sel); let HasClamp = 0; let HasOMod = 0; } diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td index 2a9992087ca9..09346f400d71 100644 --- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td @@ -39,7 +39,7 @@ class VOP3_VOP3PInst<string OpName, VOPProfile P, bit UseTiedOutput = 0, // class constraints. !if(UseTiedOutput, (ins clampmod:$clamp, VGPR_32:$vdst_in), (ins clampmod0:$clamp))), - (ins op_sel:$op_sel, op_sel_hi:$op_sel_hi)); + (ins op_sel0:$op_sel, op_sel_hi0:$op_sel_hi)); let Constraints = !if(UseTiedOutput, "$vdst = $vdst_in", ""); let DisableEncoding = !if(UseTiedOutput, "$vdst_in", ""); _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
