[llvm-branch-commits] [llvm] RuntimeLibcalls: Invert handling of 64-bit only libcalls (PR #148571)

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/148571 >From 2f195defcde58603936e5e6d668373708607b773 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 14 Jul 2025 14:53:08 +0900 Subject: [PATCH] RuntimeLibcalls: Invert handling of 64-bit only libcalls Switch

[llvm-branch-commits] [llvm] RuntimeLibcalls: Invert handling of 64-bit only libcalls (PR #148571)

https://github.com/arsenm ready_for_review https://github.com/llvm/llvm-project/pull/148571 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] RuntimeLibcalls: Invert handling of 64-bit only libcalls (PR #148571)

llvmbot wrote: @llvm/pr-subscribers-llvm-ir Author: Matt Arsenault (arsenm) Changes Switch the default set to exclude these conditionally available calls, so they are opt-in instead of opt-out. --- Full diff: https://github.com/llvm/llvm-project/pull/148571.diff 2 Files Affected: - (mo

[llvm-branch-commits] [llvm] RuntimeLibcalls: Invert handling of 64-bit only libcalls (PR #148571)

arsenm wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/148571?utm_source=stack-comment-downstack-mergeability-warning";

[llvm-branch-commits] [llvm] RuntimeLibcalls: Invert handling of 64-bit only libcalls (PR #148571)

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/148571 Switch the default set to exclude these conditionally available calls, so they are opt-in instead of opt-out. >From 650ac1eabb74647ae7ce6a653f6159d269818511 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mo

[llvm-branch-commits] [llvm] [CodeGen][NPM] Read TargetMachine's EnableIPRA option (PR #148108)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148108 >From 837ec7b0b82b939d87000bf12b7e22705c1c31b7 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:00:55 +0530 Subject: [PATCH 1/2] [CodeGen][NPM] Read TargetMachine's EnableIPRA option --- llvm

[llvm-branch-commits] [llvm] [CodeGen][NPM] Register Function Passes (PR #148109)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148109 >From 24e03050c25d4c480e8e4540452495a908aca29b Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:03:19 +0530 Subject: [PATCH] [CodeGen][NPM] Register Function Passes --- .../llvm/Passes/Machin

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148115 >From 358f2e2b2aa99ce56ac8d24ff4d88cfa9bcb2327 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:53:39 +0530 Subject: [PATCH] [AMDGPU][NPM] Add isRequired to passes missing it --- llvm/include

[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148114 >From 3fc8b6ea10eb633a208cedbe21656d3fe95698ee Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:38:26 +0530 Subject: [PATCH] [CodeGen][NPM] Stitch up loop passes in codegen pipeline --- llvm/

[llvm-branch-commits] [llvm] [CodeGen][NPM] Account inserted passes for -start/stop options (PR #148111)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148111 >From 245b1cd1df9bb2cae6d36428d30c4578fea0fd8b Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:24:23 +0530 Subject: [PATCH 1/2] [CodeGen][NPM] Account inserted passes for -start/stop options

[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148113 >From 6b203cd5f6d6786dc2ddf8c5fb0e20b004c80c9b Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:50:27 +0530 Subject: [PATCH] [CodeGen][NPM] Clear MachineFunctions without using PA --- .../llv

[llvm-branch-commits] [llvm] [CodeGen][NPM] Register Function Passes (PR #148109)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148109 >From 24e03050c25d4c480e8e4540452495a908aca29b Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:03:19 +0530 Subject: [PATCH] [CodeGen][NPM] Register Function Passes --- .../llvm/Passes/Machin

[llvm-branch-commits] [llvm] [CodeGen][NPM] Read TargetMachine's EnableIPRA option (PR #148108)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148108 >From 837ec7b0b82b939d87000bf12b7e22705c1c31b7 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:00:55 +0530 Subject: [PATCH 1/2] [CodeGen][NPM] Read TargetMachine's EnableIPRA option --- llvm

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Fill in addPreSched2 passes (PR #148112)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148112 >From fdd06a88e3a53f98fe3eaba9d70e1cf8913e Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:26:16 +0530 Subject: [PATCH] [AMDGPU][NPM] Fill in addPreSched2 passes --- llvm/lib/Target/AMDG

[llvm-branch-commits] [llvm] [CodeGen][NPM] Stitch up loop passes in codegen pipeline (PR #148114)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148114 >From 3fc8b6ea10eb633a208cedbe21656d3fe95698ee Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:38:26 +0530 Subject: [PATCH] [CodeGen][NPM] Stitch up loop passes in codegen pipeline --- llvm/

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Fill in addPreSched2 passes (PR #148112)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148112 >From fdd06a88e3a53f98fe3eaba9d70e1cf8913e Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:26:16 +0530 Subject: [PATCH] [AMDGPU][NPM] Fill in addPreSched2 passes --- llvm/lib/Target/AMDG

[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148115 >From 358f2e2b2aa99ce56ac8d24ff4d88cfa9bcb2327 Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 18:53:39 +0530 Subject: [PATCH] [AMDGPU][NPM] Add isRequired to passes missing it --- llvm/include

[llvm-branch-commits] [llvm] [CodeGen][NPM] Clear MachineFunctions without using PA (PR #148113)

https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/148113 >From 6b203cd5f6d6786dc2ddf8c5fb0e20b004c80c9b Mon Sep 17 00:00:00 2001 From: vikhegde Date: Thu, 10 Jul 2025 16:50:27 +0530 Subject: [PATCH] [CodeGen][NPM] Clear MachineFunctions without using PA --- .../llv

[llvm-branch-commits] [CodeGen] Add 2 subtarget hooks canLowerToZeroCycleReg[Move|Zeroing] (PR #148428)

@@ -673,3 +673,84 @@ bool AArch64Subtarget::isX16X17Safer() const { bool AArch64Subtarget::enableMachinePipeliner() const { return getSchedModel().hasInstrSchedModel(); } + +bool AArch64Subtarget::isRegInClass(const MachineInstr *MI, const Register &Reg, +

[llvm-branch-commits] [CodeGen] Add 2 subtarget hooks canLowerToZeroCycleReg[Move|Zeroing] (PR #148428)

@@ -185,6 +185,48 @@ class LLVM_ABI TargetSubtargetInfo : public MCSubtargetInfo { return false; } + /// Returns true if CopyMI can be lowered to a zero cycle register move. arsenm wrote: Can you avoid adding new hooks for this? Isn't this inferable f

[llvm-branch-commits] [CodeGen] Prevent register coalescer rematerialization based on target (PR #148430)

@@ -0,0 +1,174 @@ +# RUN: llc -o - -mtriple=arm64-linux-gnu -run-pass=register-coalescer -verify-coalescing %s | FileCheck %s -check-prefixes=NOTCPU-LINUX +# RUN: llc -o - -mtriple=arm64-apple-macosx -mcpu=generic -run-pass=register-coalescer -verify-coalescing %s | FileCheck %s

[llvm-branch-commits] [CodeGen] Prevent register coalescer rematerialization based on target (PR #148430)

@@ -1400,6 +1403,12 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP, if (!Edit.canRematerializeAt(RM, ValNo, CopyIdx)) return false; + if (!TII->shouldReMaterializeTrivialRegDef(CopyMI, DstReg, SrcReg)) { arsenm wrote: Missi

[llvm-branch-commits] [llvm] [AMDGPU] Intrinsic for launching whole wave functions (PR #145859)

https://github.com/perlfu approved this pull request. LGTM But I am unsure if request for tests from @arsenm is fully satisfied. https://github.com/llvm/llvm-project/pull/145859 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org h

[llvm-branch-commits] [CodeGen] Prevent register coalescer rematerialization based on target (PR #148430)

tomershafir wrote: This is part of a patch series: * https://github.com/llvm/llvm-project/pull/148430 * https://github.com/llvm/llvm-project/pull/148429 * https://github.com/llvm/llvm-project/pull/148428 * https://github.com/llvm/llvm-project/pull/148427 https://github.com/llvm/llvm-project/pul

[llvm-branch-commits] [CodeGen] Add target hook shouldReMaterializeTrivialRegDef (PR #148429)

tomershafir wrote: This is part of a patch series: * https://github.com/llvm/llvm-project/pull/148430 * https://github.com/llvm/llvm-project/pull/148429 * https://github.com/llvm/llvm-project/pull/148428 * https://github.com/llvm/llvm-project/pull/148427 https://github.com/llvm/llvm-project/pul

[llvm-branch-commits] [CodeGen] Add 2 subtarget hooks canLowerToZeroCycleReg[Move|Zeroing] (PR #148428)

tomershafir wrote: This is part of a patch series: * https://github.com/llvm/llvm-project/pull/148430 * https://github.com/llvm/llvm-project/pull/148429 * https://github.com/llvm/llvm-project/pull/148428 * https://github.com/llvm/llvm-project/pull/148427 https://github.com/llvm/llvm-project/pul

[llvm-branch-commits] [CodeGen] Prevent register coalescer rematerialization based on target (PR #148430)

llvmbot wrote: @llvm/pr-subscribers-backend-aarch64 Author: Tomer Shafir (tomershafir) Changes This change makes the register coalescer prevent rematerialization of a trivial def for a move instruction, if the target guides against it, based on the new target hook `shouldReMaterializeTri

[llvm-branch-commits] [CodeGen] Add 2 subtarget hooks canLowerToZeroCycleReg[Move|Zeroing] (PR #148428)

llvmbot wrote: @llvm/pr-subscribers-backend-aarch64 Author: Tomer Shafir (tomershafir) Changes Adds 2 subtarget hooks `canLowerToZeroCycleRegMove` and `canLowerToZeroCycleRegZeroing` to enable query if an instruction can be lowered to a zero cycle instruction. The logic depends on the m

[llvm-branch-commits] [CodeGen] Prevent register coalescer rematerialization based on target (PR #148430)

llvmbot wrote: @llvm/pr-subscribers-llvm-regalloc Author: Tomer Shafir (tomershafir) Changes This change makes the register coalescer prevent rematerialization of a trivial def for a move instruction, if the target guides against it, based on the new target hook `shouldReMaterializeTrivi

[llvm-branch-commits] [CodeGen] Add target hook shouldReMaterializeTrivialRegDef (PR #148429)

llvmbot wrote: @llvm/pr-subscribers-backend-aarch64 Author: Tomer Shafir (tomershafir) Changes Adds a target hook `shouldReMaterializeTrivialRegDef` that enables target to specify wether rematerialization of the copy is beneficial. This patch also provide an implementation for AArch64 ba

[llvm-branch-commits] [CodeGen] Add target hook shouldReMaterializeTrivialRegDef (PR #148429)

https://github.com/tomershafir created https://github.com/llvm/llvm-project/pull/148429 Adds a target hook `shouldReMaterializeTrivialRegDef` that enables target to specify wether rematerialization of the copy is beneficial. This patch also provide an implementation for AArch64 based on the ne

[llvm-branch-commits] [CodeGen] Prevent register coalescer rematerialization based on target (PR #148430)

https://github.com/tomershafir created https://github.com/llvm/llvm-project/pull/148430 This change makes the register coalescer prevent rematerialization of a trivial def for a move instruction, if the target guides against it, based on the new target hook `shouldReMaterializeTrivialRegDef`.

[llvm-branch-commits] [CodeGen] Add 2 subtarget hooks canLowerToZeroCycleReg[Move|Zeroing] (PR #148428)

https://github.com/tomershafir created https://github.com/llvm/llvm-project/pull/148428 Adds 2 subtarget hooks `canLowerToZeroCycleRegMove` and `canLowerToZeroCycleRegZeroing` to enable query if an instruction can be lowered to a zero cycle instruction. The logic depends on the microarchitect