================
@@ -673,3 +673,84 @@ bool AArch64Subtarget::isX16X17Safer() const {
bool AArch64Subtarget::enableMachinePipeliner() const {
return getSchedModel().hasInstrSchedModel();
}
+
+bool AArch64Subtarget::isRegInClass(const MachineInstr *MI, const Register
&Reg,
+ const TargetRegisterClass *TRC) const {
+ if (Reg.isPhysical()) {
+ return TRC->contains(Reg);
+ } else {
----------------
arsenm wrote:
No else after return
https://github.com/llvm/llvm-project/pull/148428
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