llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-aarch64 Author: Tomer Shafir (tomershafir) <details> <summary>Changes</summary> Adds a target hook `shouldReMaterializeTrivialRegDef` that enables target to specify wether rematerialization of the copy is beneficial. This patch also provide an implementation for AArch64 based on the new subtarget hooks `canLowerToZeroCycleReg[Move|Zeroing]`. It prepares for a register coalescer optimization to prevent rematerialization of moves where the target supports ZCM. --- Full diff: https://github.com/llvm/llvm-project/pull/148429.diff 3 Files Affected: - (modified) llvm/include/llvm/CodeGen/TargetInstrInfo.h (+16) - (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.cpp (+10) - (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.h (+4) ``````````diff diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h index b5b83c7ff1164..4a5b2fb0dd613 100644 --- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h +++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h @@ -418,6 +418,22 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo { return true; } + /// Returns true if CopyMI should be considered for register + /// definition rematerialization. Otherwise, returns false. + /// + /// Rematerialization can replace a source register with its value + /// from its definition. Its applied in the register coalescer, + /// after instruction selection and before register allocation. + /// + /// Subtargets can override this method to classify rematerialization + /// candidates. Note that this cannot be defined in tablegen because it + /// operates at a higher level. + virtual bool shouldReMaterializeTrivialRegDef(const MachineInstr *CopyMI, + const Register &DestReg, + const Register &SrcReg) const { + return true; + } + /// Re-issue the specified 'original' instruction at the /// specific location targeting a new destination register. /// The register in Orig->getOperand(0).getReg() will be substituted by diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index c1474773faa76..1f616440c3635 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -1029,6 +1029,13 @@ bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const { } } +bool AArch64InstrInfo::shouldReMaterializeTrivialRegDef( + const MachineInstr *CopyMI, const Register &DestReg, + const Register &SrcReg) const { + return !Subtarget.canLowerToZeroCycleRegMove(CopyMI, DestReg, SrcReg) && + !Subtarget.canLowerToZeroCycleRegZeroing(CopyMI, DestReg, SrcReg); +} + bool AArch64InstrInfo::isFalkorShiftExtFast(const MachineInstr &MI) { switch (MI.getOpcode()) { default: @@ -5025,6 +5032,9 @@ void AArch64InstrInfo::copyGPRRegTuple(MachineBasicBlock &MBB, } } +/// NOTE: must maintain consistency with +/// `AArch64Subtarget::canLowerToZeroCycleRegMove` and +/// `AArch64Subtarget::canLowerToZeroCycleRegZeroing`. void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h index 7c255da333e4b..e858e93cab2a4 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -189,6 +189,10 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo { bool isAsCheapAsAMove(const MachineInstr &MI) const override; + bool shouldReMaterializeTrivialRegDef(const MachineInstr *CopyMI, + const Register &DestReg, + const Register &SrcReg) const override; + bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override; `````````` </details> https://github.com/llvm/llvm-project/pull/148429 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
