_init_proc':
> arch/powerpc/kernel/eeh.c:1173:37: error: 'powerpc_debugfs_root' \
> undeclared (first use in this function)
> arch/powerpc/kernel/eeh.c:1173:37: note: each undeclared identifier \
> is reported only once for each function it appears in
>
> Reported-
> powerpc/pseries: relocate "config DTL" so KConfig nests properly
I don't know what that means. Can you describe it in more detail?
Mikey
On Mon, 2014-05-12 at 20:09 -0700, Cody P Schafer wrote:
> Signed-off-by: Cody P Schafer
> ---
> arch/powerpc/platforms/pseries/Kconfig | 20 ++--
On Tue, 2014-05-13 at 00:12 -0700, Cody P Schafer wrote:
> On 05/12/2014 11:23 PM, Michael Neuling wrote:
> >> powerpc/pseries: relocate "config DTL" so KConfig nests properly
> >
> > I don't know what that means. Can you describe it in more detail?
>
> s390 actually screwed that, though it got away because
> there's a bit in HWCAP to signal transactions support. See:
>
> https://sourceware.org/ml/gdb-patches/2013-11/msg00080.html
>
> Are you adding something to HWCAP too?
Yes but it's in HWCAP2
Mikey
> So in sum, it very much looks like the intention is for
> PTRACE_GETREGSET/PTRACE_SETREGSET to return ENODEV in the
> case the regset doesn't exist on the running machine, and then
> it looks like at least x86 works that way.
Good point... agreed. We should ENODEV when we don't have TM hardware
This patch series implements split core mode on POWER8. This enables up to 4
subcores per core which can each independently run guests (per guest SPRs like
SDR1, LPIDR etc are replicated per subcore). Lots more documentation on this
feature in the code and commit messages.
Most of this code is i
identical mechanism to block split core, rework the
secondary inhibit code to be a "HV KVM is active" check. We can then use
that in both the cpu hotplug code and the upcoming split core code.
Signed-off-by: Michael Ellerman
Signed-off-by: Michael Neuling
Acked-by: Alexander Graf
Acke
deal
with the interrupt later.
Signed-off-by: Michael Ellerman
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/processor.h | 2 +-
arch/powerpc/kernel/idle_power7.S| 9 +
arch/powerpc/platforms/powernv/smp.c | 2 +-
3 files changed, 11 insertions(+), 2 deletions(-)
diff
a guest.
Unlike threads_per_core which is fixed at boot, threads_per_subcore can
change while the system is running. Most code will not want to use
threads_per_subcore.
Signed-off-by: Michael Ellerman
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/cputhreads.h | 7 +++
arch
to
online cpus which are not the primary thread within their *sub* core.
On POWER7 and other systems that do not support split core,
threads_per_subcore == threads_per_core and so the check is equivalent.
Signed-off-by: Michael Ellerman
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel
given the current split
core mode.
Although threads_per_subcore can change during the life of the system,
the commit that enables that will ensure that threads_per_subcore does
not change during the life of a KVM VM.
Signed-off-by: Michael Ellerman
Signed-off-by: Michael Neuling
Acked-by
by paulus. The rest by mikey and mpe.
Signed-off-by: Michael Ellerman
Signed-off-by: Michael Neuling
Signed-off-by: Srivatsa S. Bhat
Signed-off-by: Mahesh Salgaonkar
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/reg.h | 9 +
arch/powerpc/platforms/powernv
On Fri, 2014-05-23 at 11:53 +0200, Alexander Graf wrote:
> On 23.05.14 10:15, Michael Neuling wrote:
> > This patch series implements split core mode on POWER8. This enables up to
> > 4
> > subcores per core which can each independently run guests (per guest SPRs
> &g
> >> Also, is there any performance penalty associated with split core mode?
> >> If not, could we just always default to split-by-4 on POWER8 bare metal?
> > Yeah, there is a performance hit . When you are split (ie
> > subcores_per_core = 2 or 4), the core is stuck in SMT8 mode. So if you
> > o
Alex,
> >> If it's the latter, we could just have ppc64_cpu --smt=x also set the
> >> subcore amount in parallel to the thread count.
> > FWIW on powernv we just nap the threads on hotplug.
> >
> >> The reason I'm bringing this up is that I'm not quite sure who would be
> >> the instance doing the
in the KVM code, use these defines when we call
h_set_mode. No functional change.
Signed-off-by: Michael Neuling
--
This depends on the KVM h_set_mode patches.
diff --git a/arch/powerpc/include/asm/plpar_wrappers.h
b/arch/powerpc/include/asm/plpar_wrappers.h
index 12c32c5..67859ed 100644
--- a/
On Fri, 2014-05-30 at 18:56 +1000, Michael Ellerman wrote:
> On Thu, 2014-05-29 at 17:45 +1000, Michael Neuling wrote:
> > > > +/* Values for 2nd argument to H_SET_MODE */
> > > > +#define H_SET_MODE_RESOURCE_SET_CIABR1
> > > > +#defin
>>>
>>> Which header are these coming from, and why aren't we including it? And
is it
>>> going to still build with CONFIG_KVM=n?
>>
>> From include/asm/hvcall.h in the h_set_mode patch set I sent before.
>>
>> And yes it compiles with CONFIG_KVM=n fine.
>
>
> Please split that patch into one that
On Fri, 2014-05-30 at 17:40 +0530, Anshuman Khandual wrote:
> This patch enables support for hardware instruction breakpoints on POWER8 with
> the help of a new register called CIABR (Completed Instruction Address
> Breakpoint
> Register). With this patch, single hardware instruction breakpoint ca
powernv.
Signed-off-by: Michael Neuling
---
drivers/cpuidle/cpuidle-powernv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cpuidle/cpuidle-powernv.c
b/drivers/cpuidle/cpuidle-powernv.c
index 719f6fb..7f7798e 100644
--- a/drivers/cpuidle/cpuidle-powernv.c
+++ b
best case IPI latency between two threads dropped
from 894ns to 512ns.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/cpu_setup_power.S | 2 ++
arch/powerpc/platforms/powernv/smp.c | 6 ++
arch/powerpc/sysdev/xics/icp-native.c | 9 -
3 files changed, 16 insertions(+), 1
On Mon, 2014-06-02 at 14:59 +0200, Stephane Eranian wrote:
> On Wed, May 28, 2014 at 10:04 AM, Anshuman Khandual
> wrote:
> > On 05/27/2014 05:39 PM, Stephane Eranian wrote:
> >> I have been looking at those patches and ran some tests.
> >> And I found a few issues so far.
> >>
> >> I am running:
On Wed, 2014-06-04 at 18:03 +1000, Michael Ellerman wrote:
> On Mon, 2014-06-02 at 16:57 +1000, Michael Neuling wrote:
> > This patch enables POWER8 doorbell IPIs on powernv.
> >
> > Since doorbells can only IPI within a core, we test to see when we can use
> > doorbe
On Wed, 2014-06-04 at 17:31 +1000, Michael Ellerman wrote:
> Hi Sam,
>
> Comments inline ..
Ditto
>
> On Wed, 2014-06-04 at 13:33 +1000, Sam Bobroff wrote:
> > Correct the DSCR SPR becoming temporarily corrupted when a task is
> > context switched when within a transaction. It is corrected
best case IPI latency between two threads dropped
from 894ns to 512ns.
Signed-off-by: Michael Neuling
---
v2:
Adds select of PPC_DOORBELL for PSERIES and POWERNV as suggested by mpe.
diff --git a/arch/powerpc/kernel/cpu_setup_power.S
b/arch/powerpc/kernel/cpu_setup_power.S
index 1557e7c
liable via this status property before putting
it in the present map.
Signed-off-by: Michael Neuling
Tested-by: Anton Blanchard
cc: sta...@vger.kernel.org
---
arch/powerpc/kernel/setup-common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/setup-common.c
This enables POWER8 doorbells on powernv.
v2 changes:
Only clear LPCR_PECE1 in fastsleep_loop() leave all other bits untouched.
Add "select PPC_DOORBELL" for CONFIG PPC_POWERNV/PSERIES
Michael Neuling (2):
powerpc/cpuidle: Only clear LPCR decrementer wakeup bit on fast s
powernv. Also we no longer clear the MER bit as it should never be set in the
host anyway.
Signed-off-by: Michael Neuling
---
drivers/cpuidle/cpuidle-powernv.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/cpuidle/cpuidle-powernv.c
b/drivers/cpuidle/cpuidle
best case IPI latency between two threads dropped
from 894ns to 512ns.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/cpu_setup_power.S | 2 ++
arch/powerpc/platforms/powernv/Kconfig | 1 +
arch/powerpc/platforms/powernv/smp.c | 6 ++
arch/powerpc/platforms/pseries/Kconfig | 1
This enables POWER8 doorbells on powernv.
v2 changes:
Only clear LPCR_PECE1 in fastsleep_loop() leave all other bits untouched.
Add "select PPC_DOORBELL" for CONFIG PPC_POWERNV/PSERIES
Michael Neuling (2):
powerpc/cpuidle: Only clear LPCR decrementer wakeup bit on fast s
powernv. Also we no longer clear the MER bit as it should never be set in the
host anyway.
Signed-off-by: Michael Neuling
---
drivers/cpuidle/cpuidle-powernv.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/cpuidle/cpuidle-powernv.c
b/drivers/cpuidle/cpuidle
best case IPI latency between two threads dropped
from 894ns to 512ns.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/cpu_setup_power.S | 2 ++
arch/powerpc/platforms/powernv/Kconfig | 1 +
arch/powerpc/platforms/powernv/smp.c | 6 ++
arch/powerpc/platforms/pseries/Kconfig | 1
On Mon, 2014-06-23 at 12:14 +1000, Gavin Shan wrote:
> The patch implements one OPAL firmware sysfs file to support PCI error
> injection: "/sys/firmware/opal/errinjct", which will be used like the
> way described as follows.
>
> According to PAPR spec, there are 3 RTAS calls related to error inje
>
> Signed-off-by: Preeti U Murthy
Acked-by: Michael Neuling
> ---
>
> arch/powerpc/kernel/idle_power7.S |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/kernel/idle_power7.S
> b/arch/powerpc/kernel/idle_power7.S
> index 24
On Tue, 2014-07-01 at 10:52 +1000, Michael Ellerman wrote:
> On Mon, 2014-06-30 at 11:54 +0530, Preeti U Murthy wrote:
> > Commit 8d6f7c5a: "powerpc/powernv: Make it possible to skip the IRQHAPPENED
> > check in power7_nap()" added code that prevents even cores which enter sleep
> > on idle, from c
On Jul 17, 2014 9:11 PM, "Benjamin Herrenschmidt"
wrote:
>
> > >
> > >> Outstanding Issues
> > >> ==
> > >> (1) Running DSCR register value inside a transaction does not seem
to be saved
> > >> at thread.dscr when the process stops for ptrace examination.
> > >
> > > Hey Ben,
>
On Fri, 2014-07-18 at 11:41 +0930, Joel Stanley wrote:
> These processors do not currently support doorbell IPIs, so remove them
> from the feature list if we are at DD 1.xx for the 0x004d part.
We GAed with DD2.1 and generally we don't upstream anything that isn't
GAed. Plus, if you wanna go dow
On Wed, 2014-08-06 at 20:16 +0530, Aneesh Kumar K.V wrote:
> "Aneesh Kumar K.V" writes:
>
> > If we know that user address space has never executed on other cpus
> > we could use tlbiel.
> >
> > Signed-off-by: Aneesh Kumar K.V
>
> Now checking against flush_hash_page, I am wondering whether I n
than adding any.
>
> Regardless they should all be in both masks so as to avoid any future
> bugs when the set of ALWAYS/POSSIBLE bits changes, or the masks
> themselves change.
>
> Signed-off-by: Michael Ellerman
CCing Joel but FWIW
Acked-by: Michael Neuling
> ---
>
Currently there is no way to generically check if an OPAL call exists or not
from the host kernel.
This adds an OPAL call opal_check_token() which tells you if the given token is
present in OPAL or not.
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/opal.h| 7
Check that the OPAL_RTC_READ token exists before we use the OPAL RTC.
Refactors the code a little to merge error paths.
This avoids littering the OPAL console with:
"OPAL: Called with bad token 3".
Signed-off-by: Michael Neuling
---
arch/powerpc/platforms/powernv/opal-
Check that the OPAL_ELOG_READ token exists before initalising the elog
infrastructure.
This avoids littering the OPAL console with:
"OPAL: Called with bad token 74"
Signed-off-by: Michael Neuling
---
arch/powerpc/platforms/powernv/opal-elog.c | 4
1 file changed, 4 insertion
Check that the OPAL_DUMP_READ token exists before initalising the elog
infrastructure.
This avoids littering the OPAL console with:
"OPAL: Called with bad token 91"
Signed-off-by: Michael Neuling
---
arch/powerpc/platforms/powernv/opal-dump.c | 4
1 file changed, 4 insertion
This cleans up kvmppc_load/save_fp. It removes unnecessary isyncs. It also
removes the unnecessary resetting of the MSR bits on exit of kvmppc_save_fp.
Signed-off-by: Michael Neuling
Signed-off-by: Paul Mackerras
---
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 2 --
1 file changed, 2 deletions
Add 'r' to register name r2 in kvmppc_hv_enter.
Also update comment at the top of kvmppc_hv_enter to indicate that R2/TOC is
non-volatile.
Signed-off-by: Michael Neuling
Signed-off-by: Paul Mackerras
---
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 3 ++-
1 file changed, 2 insert
On Tue, 2014-08-19 at 15:24 +1000, Paul Mackerras wrote:
> On Tue, Aug 19, 2014 at 02:59:29PM +1000, Michael Neuling wrote:
> > This cleans up kvmppc_load/save_fp. It removes unnecessary isyncs.
>
> NAK - they are necessary on PPC970, which we (still) support. You
> could put
Anton Blanchard wrote:
>
> If TM is not active there is no need to print PACATMSCRATCH
> so we can save ourselves a line.
>
> Signed-off-by: Anton Blanchard
Acked-by: Michael Neuling
> ---
>
> Index: b/arch/
in setcontext (ie. a small context without
VSX but with MSR VSX set), the kernel will refuse the context. This situation
has been reported by the glibc community.
Based on patch from Carlos O'Donell.
Tested-by: Haren Myneni
Signed-off-by: Michael Neuling
Cc: sta...@vger.kernel.org
---
arch/p
he -mbig-endian option before
adding it.
I've not done the same thing in the little endian case as if
-mlittle-endian doesn't exist, we probably want to fail quickly as you
probably have an old big endian compiler.
Signed-off-by: Michael Neuling
diff --git a/arch/powerpc/Makefile b/ar
chroma_defconfig is horribly broken currently, so add a bunch of
#includes to fix it.
Signed-off-by: Michael Neuling
---
So when are we dropping arch/powerpc/platforms/wsp?
diff --git a/arch/powerpc/platforms/wsp/chroma.c
b/arch/powerpc/platforms/wsp/chroma.c
index 8ef53bc..aaa46b3 100644
Carlos O'Donell wrote:
> On 11/21/2013 06:33 AM, Michael Ellerman wrote:
> > On Wed, Nov 20, 2013 at 04:18:54PM +1100, Michael Neuling wrote:
> >> The VSX MSR bit in the user context indicates if the context contains VSX
> >> state. Currently we set this when th
's not. If the returned context is then used in setcontext
(ie. a small context without VSX but with MSR VSX set), the kernel will
refuse the context. This situation has been reported by the glibc
community.
Based on patch from Carlos O'Donell.
Tested-by: Haren Myneni
Signed-off-by:
In a recent patch:
commit c13f20ac48328b05cd3b8c19e31ed6c132b44b42
Author: Michael Neuling
powerpc/signals: Mark VSX not saved with small contexts
We fixed an issue but an improved solution was later discussed after the patch
was merged.
Firstly, this patch doesn't handle the
Currently we continue to poll get/set_rtc_time even when we know they
are not working.
This changes it so that if it fails at boot time we remove the ppc_md
get/set_rtc_time hooks so that we don't end up polling known broken
calls.
Signed-off-by: Michael Neuling
diff --git a/arch/po
ned-off-by: Michael Neuling
cc: sta...@vger.kernel.org
diff --git a/arch/powerpc/include/asm/exception-64s.h
b/arch/powerpc/include/asm/exception-64s.h
index 894662a..243ce69 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -284,7 +284,7 @@
I'm not near my machine to test but looks good.
Thanks,
Mikey
On 22 Jan 2014 08:56, "Andreas Schwab" wrote:
> This fixes a logic error that caused a failure to update the hw breakpoint
> registers when not using the hw-breakpoint interface.
>
> Signed-off-by: Andreas Schwab
> ---
> arch/powerp
Stewart Smith wrote:
> This fixes a bug where we would get two events from OPAL with DUMP_AVAIL
> set (which is valid for OPAL to do) and in the second run of extract_dump()
> we would fail to free the memory previously allocated for the dump
> (leaking ~6MB+) as well as on the second dump_read_d
Stephen Rothwell wrote:
> Fixes this build error:
>
> arch/powerpc/kernel/exceptions-64s.S: Assembler messages:
> arch/powerpc/kernel/exceptions-64s.S:1312: Error: attempt to move .org
> backwards
>
> Signed-off-by: Stephen Rothwell
Builds and boots for me
Acked-of
tbegin
li r0, 2
sc
Kudos to Adhemerval Zanella Neto for finding this.
Signed-off-by: Michael Neuling
cc: Adhemerval Zanella Neto
cc: sta...@vger.kernel.org
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 8d4c247f1..af064d2 100644
The facility unavailable exception can be triggered from userspace by
accessing PMU registers when EBB is not enabled. This causes the
included pr_err() to run, hence spamming the kernel log buffer.
This avoids this by rate limiting these messages.
Signed-off-by: Michael Neuling
---
We can
obably not what you want [-Werror]
arch/powerpc/include/asm/opal.h:896:14: error: 'struct notifier_block' declared
inside parameter list [-Werror]
This is due to a missing include which is added here.
Signed-off-by: Michael Neuling
diff --git a/arch/powerpc/include/asm/opal.h b/arch
These are always breaking and I feel like I'm the only one fixing them
and I don't even have one of these boards so let's just remove them.
They are also broken right now in linux-next when compiling modules.
Signed-off-by: Michael Neuling
diff --git a/arch/powerpc/configs/mpc85
Scott,
> On Tue, 2014-03-25 at 12:15 +1100, Michael Neuling wrote:
> > These are always breaking and I feel like I'm the only one fixing them
> > and
>
> Always? Please elaborate.
Maybe once every 2-3 months I have to send a fix up for them.
> > I don't e
is is never set now
that we explictly write the TM sprs in tm_recheckpoint.
Signed-off-by: Michael Neuling
cc: sta...@vger.kernel.org
---
arch/powerpc/kernel/process.c | 30 +-
arch/powerpc/kernel/signal_32.c | 2 ++
arch/powerpc/kernel/signal_64.c | 2 ++
arch
We save r1 to the scratch SPR and restore it from there after the trechkpt so
saving r1 to the paca is not needed.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/tm.S | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/powerpc/kernel/tm.S b/arch/powerpc/kernel/tm.S
index 03567c0
igned-off-by: Michael Neuling
---
arch/powerpc/include/asm/reg.h | 1 +
arch/powerpc/kernel/tm.S | 38 +++---
2 files changed, 36 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1a36b8e..c0
In:
commit 742415d6b66bf09e3e73280178ef7ec85c90b7ee
Author: Michael Neuling
powerpc: Turn syscall handler into macros
We converted the syscall entry code onto macros, but in doing this we
introduced some cruft that's never run and should never have been added.
This removes that
Joel Stanley wrote:
> OPAL provides an in-memory circular buffer containing a message log
> populated with various runtime messages produced by the firmware.
>
> Provide a sysfs interface /sys/firmware/opal/messages for userspace to
> view the messages.
>
> Signed-off-by: Joel Stanley
> ---
>
Michael Neuling wrote:
> Joel Stanley wrote:
>
> > OPAL provides an in-memory circular buffer containing a message log
> > populated with various runtime messages produced by the firmware.
> >
> > Provide a sysfs interface /sys/firmware/opal/messages for user
Anshuman Khandual wrote:
> This patch adds few more ptrace request macros expanding
> the existing capability. These ptrace requests macros can
> be classified into two categories.
Why is this only an RFC?
Also, please share the test case that you wrote for this.
Mikey
>
> (1) Transactional
Anton Blanchard wrote:
> These patches apply against my last series and fix all known
> ABIv2 issues.
>
> To stress the module loader and dynamic ftrace code, I built an
> allmodconfig kernel and inserted every module I could. I found a bunch
> of bugs in the modules themselves, but in the end I
is is never set now
that we explictly write the TM sprs in tm_recheckpoint.
Signed-off-by: Michael Neuling
cc: sta...@vger.kernel.org
---
v2:
Fix bug where TM SPRs are not saved when outside a transaction.
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index a
Benjamin Herrenschmidt wrote:
> Turn them on at the same time as we allow MSR_IR/DR in the paca
> kernel MSR, ie, after the MMU has been setup enough to be able
> to handle relocated access to the linear mapping.
>
> Signed-off-by: Benjamin Herrenschmidt
> ---
> arch/powerpc/kernel/cpu_setup_p
On Thu, 2015-01-01 at 13:38 +0530, Anshuman Khandual wrote:
> On 12/20/2014 12:58 AM, Edjunior Barbosa Machado wrote:
> > On 12/08/2014 08:08 AM, Anshuman Khandual wrote:
> >> On 12/03/2014 12:18 PM, Anshuman Khandual wrote:
> >>> On 12/03/2014 10:52 AM, Michael Ellerman wrote:
> On Tue, 2014-
> > > Inside transaction both running and check pointed values can be
> > > probed independently.
> >
> > Yep, that's the idea, although setting the running values won't change
> > anything since the the translation is already doomed and will abort once
> > the cpu starts executing it.
>
> So this
On Fri, 2015-01-23 at 08:44 +1100, Michael Neuling wrote:
> > > > Inside transaction both running and check pointed values can be
> > > > probed independently.
> > >
> > > Yep, that's the idea, although setting the running values won't change
Uli,
Sorry for the slow response.
> Michael Neuling wrote on 28.01.2015 05:28:09:
>
> > Sorry, I'm rethinking this as we didn't consider user suspended
> > transactions.
> >
> > It makes sense for normal transactions but for user suspended
> > tr
On Wed, 2015-03-18 at 13:53 +0100, Ulrich Weigand wrote:
> Michael Neuling wrote on 23.02.2015 05:51:50:
>
> > Sorry for the slow response.
>
> Same here :-(
I'm going to break the cycle and respond in a few hours :-)
> > I think what you're proposing wit
On Thu, 2015-03-19 at 09:45 +1100, Michael Neuling wrote:
> On Wed, 2015-03-18 at 13:53 +0100, Ulrich Weigand wrote:
> > Michael Neuling wrote on 23.02.2015 05:51:50:
> >
> > > Sorry for the slow response.
> >
> > Same here :-(
>
> I'm goin
null_syscall.c
> indicate the cost of a system call increases by about 0.5%.
>
> Signed-off-by: Sam Bobroff
Thanks Sam!
Acked-By: Michael Neuling
> ---
> Documentation/powerpc/transactional_memory.txt | 33
>
> arch/powerpc/include/uapi/asm/t
Subcores isn't really part of the 2.07 architecture but currently we
turn it on using the 2.07 feature bit. Subcores is really a POWER8
specific feature.
This adds a new CPU_FTR bit just for subcores and moves the subcore
init code over to use this.
Signed-off-by: Michael Neuling
---
patches).
- Advertises new user features bits PPC_FEATURE2_ARCH_3_00 &
HAS_IEEE128 when on POWER9.
- Drops CPU_FTR_SUBCORE.
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/cputable.h | 14 --
arch/powerpc/include/asm/mmu-hash64.h | 1 +
arch/powerpc/include/asm/m
> > +_GLOBAL(__setup_cpu_power9)
> > + mflrr11
> > + bl __init_FSCR
> > + bl __init_PMU
> Just to keep in mind, I am not sure whether
> powerisa 3.0 support MMCRS spr, so we
> will need a feature check in __init_PMU()
> for power9.
Yeah, I'm not expecting this to work.
I'm try
On Wed, 2016-02-17 at 22:09 +1100, Michael Ellerman wrote:
> On Wed, 2016-02-17 at 16:07 +1100, Michael Neuling wrote:
>
> > Add a cputable entry for POWER9. More code is required to actually
> > boot and run on a POWER9 but this gets the base piece in which we
> > c
Add CPU table entry for POWER9
v2:
Updates based on comments from mpe:
- reuse user features from POWER8
- remove "Hacked up" from comment
- gave oprofile name POWER9
- removed untested power8 machine check hook
- used defines for tlb init code
- removed pmu init from setup code
- a
ff-by: Michael Neuling
---
arch/powerpc/include/asm/cputable.h | 3 ++-
arch/powerpc/platforms/powernv/subcore.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index b118072..a47e175 100644
--- a
Use defines for literals __init_tlb_power[78] rather than hand coding
them.
Signed-off-by: Michael Neuling
---
arch/powerpc/kernel/cpu_setup_power.S | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/cpu_setup_power.S
b/arch/powerpc/kernel
patches).
- Advertises new user features bits PPC_FEATURE2_ARCH_3_00 &
HAS_IEEE128 when on POWER9.
- Drops CPU_FTR_SUBCORE.
- Drops PMU code and machine check.
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/cputable.h | 17 +++---
arch/powerpc/include/asm/mmu-hash64.h
On Tue, 2016-02-23 at 17:21 +0100, Frederic Barrat wrote:
> From: Christophe Lombard
>
> The hcalls introduced for cxl use a possible new value:
> H_STATE (invalid state).
FWIW, this patch subject be powerpc: not cxl:
> Co-authored-by: Frederic Barrat
> Signed-off-by: Frederic Barrat
> Sign
mebase register is actually syncing correctly, but the cxl
> driver is not detecting it. Fix is to use the proper timebase-to-time
> conversion.
>
> Signed-off-by: Frederic Barrat
Looks good!
Acked-by: Michael Neuling
> Cc: # 4.3+
> ---
> drivers/misc/cxl/pci.c | 2 +-
>
On Tue, 2016-03-01 at 16:55 +1100, Cyril Bur wrote:
> Currently the assembly to save and restore Altivec registers boils down to
> a load immediate of the offset of the specific Altivec register in memory
> followed by the load/store which repeats in sequence for each Altivec
> register.
>
> This
On Wed, 2016-03-09 at 12:53 +0100, Frederic Barrat wrote:
> Function cxl_get_phys_dev() was removed from the kernel API by a
> previous patch, but it's actually dead code. Remove it.
>
> Signed-off-by: Frederic Barrat
Acked-by: Michael Neuling
> ---
> dri
On Tue, 2016-03-01 at 16:55 +1100, Cyril Bur wrote:
> Currently the assembly to save and restore VSX registers boils down to a
> load immediate of the offset of the specific VSX register in memory
> followed by the load/store which repeats in sequence for each VSX register.
>
> This patch attempt
On Wed, 2016-03-09 at 20:07 +0530, Vaibhav Jain wrote:
> Hi Ian,
>
> Sorry for getting into this discussion late. I have few suggestions.
>
> Ian Munsie writes:
> >
> > diff --git a/drivers/misc/cxl/Kconfig b/drivers/misc/cxl/Kconfig
> > index 8756d06..560412c 100644
> > --- a/drivers/misc/cxl/
On Mon, 2016-03-14 at 20:29 +0100, Frederic Barrat wrote:
> CXL driver synchronizes the PSL timebase with the CAPP during
> initialization. If it can't synchronize, then the driver currently
> fails and the cxl adapter is not usable. That behavior is a bit
> extreme for the time being, as some adap
On Tue, 2016-03-15 at 15:26 +0100, Philippe Bergheaud wrote:
> Naples CPUs have two CAPI ports.
Naples is an internal name, don't use that. Use POWER8NVL is the name
we use in the kernel.
alsi, it's a "chip" that has two CAPI ports, not the CPU.
> Configure the PSL to route data to
> the port
> > > + psl_dsnctl |= (phb_index << (63-11));
> >
> >
> > Looking at the psl docs, cappunitid in the dsndctl is bits 6 to 13.
> > So
> > why 11 here?
> >
> Because on POWER8NVL, dsndctl bit 11 == phb_index == cappunitid.
> Bits 6-10 and 12-13 do not change between POWER8 and POWER8NVL
On Wed, 2016-02-03 at 01:11 +0530, Shilpasri G Bhat wrote:
> cpu_to_chip_id() does a DT walk through to find out the chip id by
> taking a contended device tree lock. This adds an unnecessary overhead
> in a hot path. So instead of calling cpu_to_chip_id() everytime cache
> the chip ids for all co
On Sat, 2016-03-19 at 09:37 +1100, Benjamin Herrenschmidt wrote:
> On Fri, 2016-03-18 at 15:04 +1100, Michael Neuling wrote:
> >
> > static int nr_chips;
> > +static DEFINE_PER_CPU(unsigned int, chip_id);
> >
> > /*
> > * Note: The set of pstat
ail if it can't. Instead, it reports a
> status via /sys.
"...doesn't fail if it can't".. triple negative, awesome! :-P
Other than these minor nits..
Acked-by: Michael Neuling
> Signed-off-by: Frederic Barrat
> ---
>
> Patch will need a small update for n
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