On Nov 18, 2011, at 11:50 AM, Timur Tabi wrote:
> When the P1022's DIU video controller is active, the pixis must be accessed
> in "indirect" mode, which uses localbus chip select addresses.
>
> Switching between the DVI and LVDS monitor ports is handled by the pixis,
> so that switching needs t
On Feb 9, 2012, at 8:27 PM, Jia Hongtao-B38951 wrote:
> Hi Kumar,
> This series of patches have been pending for a long time.
> I'd like to know whether they are look good or not so I can do the further
> work on it.
> It's kind of emergency things for me.
> Thanks a lot for your attention.
I c
On Feb 16, 2012, at 11:21 AM, Timur Tabi wrote:
> Remove the check for CONFIG_PPC_85xx and CONFIG_PPC_86xx from fsl_guts.h.
> The check was originally intended to allow the same header file to
> be used on 85xx and 86xx systems, even though the Global Utilities
> register could be different. It
On Feb 16, 2012, at 11:21 AM, Timur Tabi wrote:
> Add a defintion of register PAMUBYPENR (offset 0x604) to the global
> utilities structure.
>
> PAMUBYPENR is the PAMU bypass enable register. It contains control
> bits for enabling bypass mode on each PAMU.
>
> Signed-off-by: Timur Tabi
> ---
On Dec 21, 2011, at 1:10 AM, Jia Hongtao wrote:
> Power supply for PCI inbound/outbound window registers is off when system
> go to deep-sleep state. We save the values of registers before suspend
> and restore to registers after resume.
>
> Signed-off-by: Jiang Yutang
> Signed-off-by: Jia Hong
On Feb 1, 2012, at 9:50 AM, Diana Craciun wrote:
> From: Diana CRACIUN
>
> The MSIIR register for each MSI bank is aliased to a different
> address. The MSI node reg property was updated to contain this
> address:
>
> e.g. reg = <0x41600 0x200 0x44140 4>;
>
> The first region contains the add
On Feb 9, 2012, at 7:41 AM, Diana Craciun wrote:
> From: Diana CRACIUN
>
> The association in the decice tree between PCI and MSI
> using fsl,msi property was an artificial one and it does
> not reflect the actual hardware.
>
> Signed-off-by: Diana CRACIUN
> ---
> arch/powerpc/boot/dts/p2041r
On Feb 27, 2012, at 6:25 AM, Paul Gortmaker wrote:
> The mpc836x_mds platform has been broken since the commit
> 6fe3264945ee63292cdfb27b6e95bc52c603bb09
>
> "netdev/phy: Use mdiobus_read() so that proper locks are taken"
>
> which caused the fsl_pq_mdio TBI autoprobe to oops. The oops
> was
On Jan 31, 2012, at 4:15 AM, Claudiu Manoil wrote:
> fsl_85xx_l2ctlr.o and fsl_85xx_cache_sram.o are built only
> if CONFIG_FSL_85XX_CACHE_SRAM is defined. The driver that
> qualifies and wants to make use of the CACHE SRAM's exported
> API (i.e. a freescale net driver) should (be able to) select
On Feb 1, 2012, at 11:05 AM, Claudiu Manoil wrote:
> CC arch/powerpc/sysdev/fsl_85xx_l2ctlr.o
> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c:209:13: error: 'THIS_MODULE' undeclared
> here (not in a function)
> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c:229:20: error: expected declaration
> specifiers
On Mar 6, 2012, at 11:20 PM, Shengzhou Liu wrote:
> From: Liu Shuo
>
> Fix the compatible string of sec 4.0 to match with CAMM driver according
> to Documentation/devicetree/bindings/crypto/fsl-sec4.txt
>
> Signed-off-by: Liu Shuo
> Signed-off-by: Shengzhou Liu
> ---
> v2: refine description
On Feb 22, 2012, at 4:20 AM, Zhao Chenhui wrote:
> From: chenhui zhao
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c |3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
applied
- k
On Feb 21, 2012, at 11:44 PM, Zhicheng Fan wrote:
> From: Zhicheng Fan
>
> The mpc85xx_rdb and mpc85xx_mds have commom define of signal multiplex for
> qe, so
> they need to go in common header, the patch abstract them to fsl_guts.h
>
> Signed-off-by: Zhicheng Fan
> ---
> arch/powerpc/includ
On Feb 21, 2012, at 11:44 PM, Zhicheng Fan wrote:
> From: Zhicheng Fan
>
> Signed-off-by: Zhicheng Fan
> ---
> arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 77 -
> 1 files changed, 76 insertions(+), 1 deletions(-)
applied
- k
__
On Feb 21, 2012, at 1:53 PM, Timur Tabi wrote:
> Remove the "select PHYS_64BIT" from the Kconfig entry for the P1022DS,
> so that large physical address support is a selectable option for non-CoreNet
> reference boards.
>
> The option is enabled in mpc85xx_[smp_]defconfig so that the default is
>
>
> diff --git a/arch/powerpc/boot/dts/bsc9131rdb.dtsi
> b/arch/powerpc/boot/dts/bsc9131rdb.dtsi
> new file mode 100644
> index 000..d274c014
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/bsc9131rdb.dtsi
> @@ -0,0 +1,179 @@
> +/*
> + * BSC9131 RDB Device Tree Source stub (no addresses or t
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> From: chenhui zhao
>
> Remove FPGA(CADMUS) macros in code. Move it to dts.
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
> arch/powerpc/boot/dts/mpc8548cds.dts |8 -
> arch/powerpc/platforms/85xx/mpc85xx_cds.c |
On Mar 14, 2012, at 5:15 AM, Zhao Chenhui wrote:
> From: chenhui zhao
>
> There is a PCI bridge(Tsi310) between the MPC8548 and a VIA
> southbridge chip.
>
> The bootloader sets the PCI bridge to open a window from 0x
> to 0x1fff on the PCI I/O space. But the kernel can't set the I/O
> res
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> From: chenhui zhao
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
> arch/powerpc/boot/dts/mpc8548cds.dts | 40 +-
> 1 files changed, 39 insertions(+), 1 deletions(-)
applied
- k
__
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> From: chenhui zhao
>
> Enable RapidIO and add rapidio and rmu nodes to dts.
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
> arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi | 16
> arch/powerpc/boot/dts/mpc8548
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> Correct ethernet1 and add ethernet2 and ethernet3.
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
> arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi |4 +++-
> 1 files changed, 3 insertions(+), 1 deletions(-)
applied
- k
__
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> * Create mpc8548cds.dtsi.
> * Move lbc, soc and pci0 nodes to mpc8548cds_32b.dtsi.
> * Change cuImage.mpc8548cds to cuImage.mpc8548cds_32b.
> * Rename mpc8548cds.dts to mpc8548cds_32b.dts.
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
On Mar 6, 2012, at 3:06 AM, Zhao Chenhui wrote:
> Create mpc8548cds_36b.dts. Support 36-bit mode.
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
> arch/powerpc/boot/dts/mpc8548cds_36b.dts | 86 ++
> 1 files changed, 86 insertions(+), 0 deletions(-)
On Feb 10, 2012, at 2:09 AM,
wrote:
> From: Liu Shuo
>
> A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
> goes down. when the link goes down, Non-posted transactions issued
> via the ATMU requiring completion result in an instruction stall.
> At the same time a machine-
On Jan 8, 2012, at 11:45 PM,
wrote:
> From: Jerry Huang
>
> For all mpc85xx DS/MDS boards, we should check the return value from
> function "fsl_add_bridge", otherwise, when pcie node status is disabled,
> the kernel will panic when perform the function "pci_find_hose_for_OF_device"
> becaus
On Nov 30, 2011, at 10:19 AM, Timur Tabi wrote:
> Commit 46d026ac ("powerpc/85xx: consolidate of_platform_bus_probe calls")
> replaced platform-specific of_device_id tables with a single function
> that probes the most of the busses in 85xx device trees. If a specific
> platform needed additiona
On Mar 16, 2012, at 3:42 PM, Scott Wood wrote:
> On 03/16/2012 03:35 PM, Kumar Gala wrote:
>> On Feb 10, 2012, at 2:09 AM,
>> wrote:
>>> +static int is_in_pci_mem_space(phys_addr_t addr)
>>> +{
>>> + struct pci_controller *hose;
&
On Feb 10, 2012, at 2:09 AM,
wrote:
> From: Liu Shuo
>
> A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe
> goes down. when the link goes down, Non-posted transactions issued
> via the ATMU requiring completion result in an instruction stall.
> At the same time a machine-
Guys,
I'm not sure what the state of the EDAC patches and latest kernel are.. I'm
going to mark the ones in patch works as 'dead' and hopefully you guys will
resend if there is still an interest.
- k
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Guys,
Are you aware of any reason that we can't call of_platform_bus_probe() or
multiple times. Timur's run into an issue in which all devices don't get
registered properly if we call of_platform_bus_probe() times with different
of_device_id struct's.
- k
_
er binding
Kumar Gala (2):
powerpc/fsl-booke: Fixup calc_cam_sz to support MMU v2
powerpc: Add initial e6500 cpu support
Liu Gang (2):
powerpc/srio: Fix the relocation errors when building with 64bit
powerpc/srio: Fix the compile errors when building with 64bit
L
On Mar 19, 2012, at 1:19 AM, Shengzhou Liu wrote:
> In some device trees of previous version, there were string "fsl,sec4.0".
> To be backward compatible with device trees, we have CAAM driver first
> check "fsl,sec-v4.0", if it fails, then check for "fsl,sec4.0".
>
> Signed-off-by: Shengzhou Li
On Mar 19, 2012, at 11:04 AM, Grant Likely wrote:
> On Fri, 16 Mar 2012 15:50:44 -0500, Timur Tabi wrote:
>> Kumar Gala wrote:
>>
>>> This seems like paper taping over the real issue. We should be able to
>>> call of_platform_bus_probe() multiple times.
&
k that p1010rdb boots and works w/my next branch.
- k
>
>
> Regards
> Poonam
>
>> -Original Message-
>> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
>> Sent: Friday, March 16, 2012 8:50 PM
>> To: Aggrwal Poonam-B10812
>> Cc: Robin Holt; U Bh
On Mar 17, 2012, at 3:39 AM, Prabhakar Kushwaha wrote:
> BSC9131RDB is a Freescale reference design board for BSC9131 SoC.The BSC9131
> is
> integrated SoC that targets Femto base station market. It combines Power
> Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F
> b
On Mar 17, 2012, at 3:58 AM, Shaveta Leekha wrote:
> Signed-off-by: Shaveta Leekha
> ---
> arch/powerpc/configs/corenet64_smp_defconfig |2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
applied, squashed to a single commit for all 4 and updated commit message
- k
___
On Mar 15, 2012, at 5:41 PM, Timur Tabi wrote:
> The "memory" clobber tells the compiler to ensure that all writes to memory
> are committed before the hypercall is made.
>
> "memory" is only necessary for hcalls where the Hypervisor will read or
> write guest memory. However, we add it to all h
On Feb 16, 2012, at 8:49 PM, Jia Hongtao wrote:
> Some MPIC implementations contain one or more blocks of message registers
> that are used to send messages between cores via IPIs. A simple API has
> been added to access (get/put, read, write, etc ...) these message registers.
> The available me
On Feb 9, 2012, at 7:41 AM, Diana Craciun wrote:
> From: Diana CRACIUN
>
> The association in the decice tree between PCI and MSI
> using fsl,msi property was an artificial one and it does
> not reflect the actual hardware.
>
> Signed-off-by: Diana CRACIUN
> ---
> arch/powerpc/boot/dts/p2041r
On Mar 20, 2012, at 1:24 AM,
wrote:
> From: Jerry Huang
>
> Signed-off-by: Jerry Huang
> ---
> changes for v2:
> - remove the lable "read-only" for DTB and kernel partition
> - remove the word "RO" or "RW" from the "lable" option
>
> arch/powerpc/boot/dts/p1020utm-pc.dtsi|
On Mar 19, 2012, at 11:06 AM, Timur Tabi wrote:
> Remove the check for CONFIG_PPC_85xx and CONFIG_PPC_86xx from fsl_guts.h.
> The check was originally intended to allow the same header file to
> be used on 85xx and 86xx systems, even though the Global Utilities
> register could be different. It
On Mar 20, 2012, at 1:24 AM,
wrote:
> From: Jerry Huang
>
> Signed-off-by: Jerry Huang
> ---
> changes for v2:
> - remove the lable "read-only" for DTB and kernel partition
> - remove the word "RO" or "RW" from the "lable" option
>
> arch/powerpc/boot/dts/p1020mbg-pc.dtsi|
On Mar 1, 2012, at 3:32 AM, Jia Hongtao wrote:
> This binding documents how the message register blocks found in some FSL
> MPIC implementations shall be represented in a device tree.
>
> Signed-off-by: Meador Inge
> Signed-off-by: Jia Hongtao
> ---
> Changes for v2:
> * Update compatible type
On Mar 21, 2012, at 12:29 PM, Kushwaha Prabhakar-B32579 wrote:
>>
>>
>> [snip]
>>
>
> ??
> Not getting you..
Just meant, I was removing parts of the patch in the email to reduce things.
>
>>> diff --git a/arch/powerpc/platforms/85xx/bsc913x_rdb.c
>>> b/arch/powerpc/platforms/85xx/bsc913x_r
On Feb 28, 2012, at 6:09 PM, Alexander Graf wrote:
> From: Scott Wood
>
> DO_KVM will need to identify the particular exception type.
>
> There is an existing set of arbitrary numbers that Linux passes,
> but it's an undocumented mess that sort of corresponds to server/classic
> exception vect
On Mar 19, 2012, at 8:02 PM, Poonam Aggrwal wrote:
> This TDM controller is available in various Freescale SOCs like MPC8315,
> P1020,
> P1022, P1010.
>
> Signed-off-by: Sandeep Singh
> Signed-off-by: Poonam Aggrwal
> ---
> Changes in v2:
> - Incorporated Scott's Review comments
> Docum
On Mar 21, 2012, at 1:19 PM, Scott Wood wrote:
> On 03/21/2012 01:04 PM, Kumar Gala wrote:
>>
>> On Feb 28, 2012, at 6:09 PM, Alexander Graf wrote:
>>
>>> From: Scott Wood
>>>
>>> DO_KVM will need to identify the particular exception type
On Mar 21, 2012, at 4:28 PM, Kent Yoder wrote:
> arch/powerpc/crypto/nx/Makefile | 11 +
> arch/powerpc/crypto/nx/nx-aes-cbc.c | 135 +
> arch/powerpc/crypto/nx/nx-aes-ccm.c | 466 ++
> arch/powerpc/crypto/nx/nx-aes-ctr.c | 175 +++
> a
On Mar 22, 2012, at 2:08 PM, Kent Yoder wrote:
> Hi Kumar,
>
>> Is there a reason this isn't in drivers/crypto/
>
> Other arch-specific dirs have their crypto subdir as well such as
> arch/s390. I was just matching that.
>
> Kent
>
>> - k
>
>From what I can tell this isn't ISA level instr
On Mar 27, 2012, at 7:16 AM, Varun Sethi wrote:
> Allocate vector numbers for MPIC internal interrupt sources (IPIs and Timers)
> in a
> separate function.
>
Explain why you are making this change.
> Signed-off-by: Varun Sethi
> ---
> arch/powerpc/include/asm/mpic.h |7 +--
> arch/po
On Mar 27, 2012, at 7:15 AM, Varun Sethi wrote:
> FSL MPIC supports 16 bit vectors so our vector number space isn't
> restricted to 256 vectors. We should use the MPIC_LARG_VECTORS flag
> while intializing the MPIC. This also prevents us from eating in to
> hardware vector number space (MSIs) wh
On Mar 27, 2012, at 7:17 AM, Varun Sethi wrote:
> All SOC device error interrupts are muxed and delivered to the core as a
> single
> MPIC error interrupt. Currently all the device drivers requiring access to
> device
> errors have to register for the MPIC error interrupt as a shared interrupt.
On Mar 27, 2012, at 8:52 AM, Sethi Varun-B16395 wrote:
>
>
>> -Original Message-----
>> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
>> Sent: Tuesday, March 27, 2012 6:55 PM
>> To: Sethi Varun-B16395
>> Cc: Linuxppc-dev@lists.ozlabs.org
>> S
On Mar 27, 2012, at 2:07 PM, Scott Wood wrote:
> On 03/27/2012 08:59 AM, Kumar Gala wrote:
>>
>> On Mar 27, 2012, at 7:17 AM, Varun Sethi wrote:
>>
>>> All SOC device error interrupts are muxed and delivered to the core as a
>>> single
>>>
On Mar 27, 2012, at 2:16 PM, Scott Wood wrote:
> On 03/27/2012 01:44 PM, Scott Wood wrote:
>> On 03/27/2012 10:21 AM, Stuart Yoder wrote:
>>> On Tue, Mar 27, 2012 at 8:30 AM, Kumar Gala
>>> wrote:
>>>>
>>>> On Mar 27, 2012, at 7:15 AM, Varu
nding on NAND or NAND+NOR mode. In 36bit mode it is shifted to
>> > 0xfff80 but it has always an eight there and never an A.
>> >
>> > Signed-off-by: Sebastian Andrzej Siewior
>> > Signed-off-by: Kumar Gala
>>
>> I am having a hard time veri
Ben,
A few minor bug fixes and missing dts updates for 3.4. There got lost in
the mix. Sorry for the delay
- k
The following changes since commit 1ce447b90f3e71c81ae59e0062bc305ef267668b:
powerpc/perf: Fix instruction address sampling on 970 and Power4 (2012-03-28
11:33:24 +1100)
are avai
On Mar 30, 2012, at 9:04 AM, Sebastian Andrzej Siewior wrote:
> On 03/29/2012 03:10 PM, Kumar Gala wrote:
>
>>> - include/configs/P1_P2_RDB.h
>>>
>>> #ifndef CONFIG_NAND_SPL
>>> #define CONFIG_SYS_NAND_BASE0xffa
On Apr 1, 2012, at 1:56 AM, Jia Hongtao wrote:
> If PCI is primary bus we should set isa_io/mem_base when parsing PCI bridge
> resources from device tree. The previous way to check the primary bus based
> on a hard-coded address named primary_phb_addr. Now we add a property named
> "fsl,has-isa"
On Apr 4, 2012, at 8:32 AM, Shawn Guo wrote:
> Kumar,
>
> Gentle ping ...
>
> Regards,
> Shawn
Was on a bit of travel to nowhere, but that's a different story.
What timeframe are you looking for this to go in? 3.4 or 3.5?
- k
>
> On Fri, Mar 30, 2012 at 01:38:56PM +0800, Shawn Guo wrote:
>
c support") collided during merge, leaving e6500's CPU
> table entry missing CPU_FTR_EMB_HV.
>
> Signed-off-by: Scott Wood
> ---
> Fixup patch for the KVM merge as requested by Marcelo.
>
> arch/powerpc/include/asm/cputable.h |2 +-
> 1 files changed
On Apr 17, 2012, at 4:39 PM, York Sun wrote:
> The timebase synchronization is only necessary if we need to reset a
> separate core. Currently only KEXEC and CPU hotplug require resetting
> a single core. The following code should be in the condition of
> CONFIG_KEXEC or CONFIG_HOTPLUG_CPU
>
>
On Apr 17, 2012, at 5:17 PM, Scott Wood wrote:
> On 04/17/2012 04:39 PM, York Sun wrote:
>> The timebase synchronization is only necessary if we need to reset a
>> separate core. Currently only KEXEC and CPU hotplug require resetting
>> a single core. The following code should be in the conditio
On Apr 17, 2012, at 11:42 PM, Anton Blanchard wrote:
>
> Older versions of gcc had issues with using -maltivec together with
> -mcpu of a non altivec capable CPU. We work around it by specifying
> -mcpu=970, but the logic is complicated.
>
> In preparation for adding more -mcpu targets, remove
On Apr 17, 2012, at 11:45 PM, Anton Blanchard wrote:
>
> Add a menu to select various 64-bit CPU targets for gcc. We
> default to -mtune=power7 and if gcc doesn't understand that we
> fallback to -mtune=power4.
>
> Signed-off-by: Anton Blanchard
> ---
Can you add a target for e5500 cpu.
- k
On Nov 30, 2011, at 10:19 AM, Timur Tabi wrote:
> Commit 46d026ac ("powerpc/85xx: consolidate of_platform_bus_probe calls")
> replaced platform-specific of_device_id tables with a single function
> that probes the most of the busses in 85xx device trees. If a specific
> platform needed additiona
On Apr 19, 2012, at 1:32 AM, Baruch Siach wrote:
> Commit ae3a197e (Disintegrate asm/system.h for PowerPC) broke build of
> assembly files when CONFIG_BOOKE_WDT is enabled as follows:
>
> AS arch/powerpc/lib/string.o
> /home/baruch/git/stable/arch/powerpc/include/asm/reg_booke.h: Assembler
On Apr 15, 2012, at 9:05 PM, Mingkai Hu wrote:
> In file included from arch/powerpc/sysdev/mpic_msgr.c:20:0:
> ~/arch/powerpc/include/asm/mpic_msgr.h: In function
> 'mpic_msgr_set_destination':
> ~/arch/powerpc/include/asm/mpic_msgr.h:117:2:
> error: implicit declaration of function 'get_hard_sm
On Apr 15, 2012, at 9:05 PM, Mingkai Hu wrote:
> Also fix issue of accessing invalid msgr pointer issue. The local
> msgr pointer in fucntion mpic_msgr_get will be accessed before
> getting a valid address which will cause kernel crash.
>
> Signed-off-by: Mingkai Hu
> ---
> arch/powerpc/sysdev/
On Apr 15, 2012, at 9:05 PM, Mingkai Hu wrote:
> Signed-off-by: Mingkai Hu
> ---
> arch/powerpc/sysdev/mpic_msgr.c |2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
applied to merge
- k
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On Apr 15, 2012, at 9:05 PM, Mingkai Hu wrote:
> Signed-off-by: Mingkai Hu
> ---
> arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi | 43 +
> arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi | 10 +
> 2 files changed, 53 insertions(+), 0 deletions(-)
> create mode 100
Ben,
Some bug fix patches for v3.4.
- k
The following changes since commit fae2e0fb24c61ca68c98d854a34732549ebc1854:
powerpc: Fix typo in runlatch code (2012-04-11 10:42:15 +1000)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git merge
On Apr 20, 2012, at 1:37 PM, Yoder Stuart-B08248 wrote:
> There was refactoring change a while back that moved
> the interrupt map down into the virtual pci bridge.
>
> example:
> 42 /* controller at 0x20 */
> 43 &pci0 {
> 44 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
>
On Apr 20, 2012, at 2:04 PM, Scott Wood wrote:
> On 04/20/2012 01:53 PM, Kumar Gala wrote:
>>
>> On Apr 20, 2012, at 1:37 PM, Yoder Stuart-B08248 wrote:
>>
>>> There was refactoring change a while back that moved
>>> the interrupt map down into t
On Jun 1, 2012, at 5:29 AM, Zhao Chenhui-B35336 wrote:
> Hi Ben and Paul,
>
> I am sorry to trouble you. It seems that Kumar is busy recently.
>
> Could you have a review on the following patches? These patches
> implement the power management support on MPC85xx platform.
>
> http://patchwork.
On Jun 4, 2012, at 8:12 AM, Olof Johansson wrote:
> Hi,
>
> On Mon, Jun 4, 2012 at 12:58 AM, Anton Blanchard wrote:
>>
>> I blame Mikey for this. He elevated my slightly dubious testcase:
>>
>> # dd if=/dev/zero of=/dev/null bs=1M count=1
>>
>> to benchmark status. And naturally we need
On Jun 19, 2012, at 8:12 AM, Guilherme Maciel Ferreira wrote:
> The struct fhci_regs (in fhci.h) is basically a redefinition
> of the struct qe_usb_ctlr (in immap_qe.h). The later struct is
> preferrable once it uses the registers names found at the
> Freescale's QUICC Engine manual. Thus it is e
On Jun 26, 2012, at 5:25 AM, Zhao Chenhui wrote:
> Do hardware timebase sync. Firstly, stop all timebases, and transfer
> the timebase value of the boot core to the other core. Finally,
> start all timebases.
>
> Only apply to dual-core chips, such as MPC8572, P2020, etc.
>
> Signed-off-by: Zha
On Jun 28, 2012, at 5:50 AM, Benjamin Herrenschmidt wrote:
> On Thu, 2012-06-28 at 11:38 +0800, Zhao Chenhui wrote:
>>
>>
>> The bootloader have done a timebase sync. If we do not need KEXEC or
>> HOTPLUG_CPU feature, it is unnecessary to do it again at boot time of
>> kernel. I only compile th
On Jun 28, 2012, at 9:36 PM, Jia Hongtao-B38951 wrote:
>
>
>> -Original Message-
>> From: Wood Scott-B07421
>> Sent: Friday, June 29, 2012 12:31 AM
>> To: Jia Hongtao-B38951
>> Cc: Wood Scott-B07421; ga...@kernel.crashing.org; Li Yang-R58472;
>> ag...@suse.de; linuxppc-dev@lists.ozlabs.
On Jun 29, 2012, at 11:01 AM, Scott Wood wrote:
> On 06/29/2012 10:57 AM, Kumar Gala wrote:
>>
>> On Jun 28, 2012, at 9:36 PM, Jia Hongtao-B38951 wrote:
>>
>>>
>>>
>>>> -Original Message-
>>>> From: Wood Scott-B07421
On Mar 16, 2012, at 11:07 AM, Timur Tabi wrote:
> Kumar Gala wrote:
>>>> Haiying said it should be ok, but I haven't tried it yet. I'll try it on
>>>> Monday.
>
>> Did you ever test this?
>
> No, I forgot all about it. I'll try i
On Sep 19, 2011, at 10:35 AM, Matias Garcia wrote:
>
> Here's the patch against 2.6.37:
>
> Change quirk_fsl_pcie_header from __init to __devinit.
>
> Signed-off-by: Matias Garcia
applied
- k
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs
On Apr 13, 2012, at 5:26 PM, Kim Phillips wrote:
> At least for crypto/IPSec, doing so provides users with a better
> performance experience out of the box.
>
> Signed-off-by: Kim Phillips
> ---
> arch/powerpc/configs/corenet32_smp_defconfig |1 +
> arch/powerpc/configs/corenet64_smp_defconf
On Apr 26, 2012, at 10:01 PM, Shengzhou Liu wrote:
> Enable MTD/NOR/NAND options by default in mpc85xx_defconfig and
> mpc85xx_smp_defconfig to support NOR, NAND flash.
>
> Signed-off-by: Shengzhou Liu
> ---
> based on master branch of
> git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/l
On Apr 16, 2012, at 8:42 PM,
wrote:
> From: Jerry Huang
>
> Add the RTC support for p1022ds
>
> Signed-off-by: Jerry Huang
> ---
> arch/powerpc/boot/dts/p1022ds.dtsi |4
> 1 files changed, 4 insertions(+), 0 deletions(-)
applied
- k
___
On May 9, 2012, at 2:53 PM, Sebastian Andrzej Siewior wrote:
> * Kumar Gala | 2012-03-31 09:48:18 [-0500]:
>
> Sorry for the delay Kumar, I though I allready done it.
>
>> Yes, please do.
> Here it comes.
>
>> From 5b3e09992615e5670fa8e432e50424466fa9ca1a M
On May 23, 2012, at 9:35 AM, Gustavo Zacarias wrote:
> Add EEPROM to the P1010RDB device tree.
> The 24c01 acts as a memory SPD so it shouldn't be overwritten without
> care.
> The 24c256 is a general purpose memory.
>
> Signed-off-by: Gustavo Zacarias
> ---
> arch/powerpc/boot/dts/p1010rdb.dts
On Jun 26, 2012, at 2:54 PM, Paul Gortmaker wrote:
> This reference board dates back to 2004, and is largely a legacy
> EOL product. The MPC8560 is a pre e500v2 CPU. The SBC8548 is
> a more modern, better e500v2 target for people to use as a
> reference board with today's kernels, should they r
On May 8, 2012, at 8:57 AM, Holger Brunck wrote:
> Signed-off-by: Holger Brunck
> cc: Heiko Schocher
> cc: Kumar Gala
> ---
> arch/powerpc/platforms/83xx/km83xx.c |2 +-
> 1 files changed, 1 insertions(+), 1 deletion
s per Freescale
> MPC8360ECE Errata document Rev.5(9/2011) item QE_ENET10.
>
> Signed-off-by: Christian Herzig
> Signed-off-by: Holger Brunck
> cc: Heiko Schocher
> cc: Kumar Gala
> ---
> arch/powerpc/platforms/83xx/km83xx.c | 98 +++---
> 1 fil
On May 8, 2012, at 8:57 AM, Holger Brunck wrote:
> Switch on UBIFS, HOTPLUG and TIPC and update the config to
> the latest kernel version.
>
> Signed-off-by: Holger Brunck
> cc: Heiko Schocher
> cc: Kumar Gala
> ---
> arch/powerpc/configs/83xx/
DS3106 clock chip.
>
> Signed-off-by: Holger Brunck
> cc: Heiko Schocher
> cc: Kumar Gala
> ---
> arch/powerpc/boot/dts/mgcoge.dts | 23 +++
> arch/powerpc/configs/mgcoge_defconfig | 12
> arch/powerpc/platforms/82xx/km82xx.c
On May 24, 2012, at 4:08 AM,
wrote:
> From: Tang Yuantian
>
> Signed-off-by: Jin Qing
> Signed-off-by: Li Yang
> Signed-off-by: Tang Yuantian
> ---
> arch/powerpc/boot/dts/p1024rdb.dtsi| 228
> arch/powerpc/boot/dts/p1024rdb_32b.dts | 87
On May 24, 2012, at 4:08 AM,
wrote:
> From: Tang Yuantian
>
> The p1024rdb has the similar feature as the p1020rdb. Therefore, p1024rdb use
> the same platform file as the p1/p2 rdb board.
> Overview of P2020RDB platform
> - DDR3 1G
> - NOR flash 16M
> - 3 Ethernet interfac
On Jun 29, 2012, at 4:41 AM, Shaohui Xie wrote:
> NAND on p2041 uses CS1 as chip select.
>
> Signed-off-by: Shaohui Xie
> ---
> arch/powerpc/boot/dts/p2041rdb.dts | 41 +++-
> 1 files changed, 40 insertions(+), 1 deletions(-)
applied
- k
__
On Apr 16, 2012, at 8:42 PM,
wrote:
> From: Jerry Huang
>
> Add the RTC support for p1022ds
>
> Signed-off-by: Jerry Huang
> ---
> arch/powerpc/boot/dts/p1022ds.dtsi |4
> 1 files changed, 4 insertions(+), 0 deletions(-)
applied
- k
___
On Apr 16, 2012, at 8:42 PM,
wrote:
> From: Jerry Huang
>
> The compatilbe 'simple-bus' is removed from the latest DTS for NAND and
> NOR flash partition, so we must add the new compatilbe support for p1022ds,
> otherwise, the kernel can't parse the partition of NOR and NAND flash.
>
> Sign
On Oct 1, 2010, at 2:05 AM, Ian Munsie wrote:
> Some PowerPC processors can be run in either big or little endian modes, some
> others can map selected pages of memory as little endian, which allows the
> same
> thing. Until now we have only supported the default big endian mode in Linux.
> This
On Oct 1, 2010, at 2:05 AM, Ian Munsie wrote:
>
> diff --git a/arch/powerpc/platforms/Kconfig.cputype
> b/arch/powerpc/platforms/Kconfig.cputype
> index d361f81..074ff12 100644
> --- a/arch/powerpc/platforms/Kconfig.cputype
> +++ b/arch/powerpc/platforms/Kconfig.cputype
> @@ -329,3 +329,19 @@ c
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