Scott,
do you think this issue also applies to MPC8377 ?
I'm in the middle of a small redesign for series production and would
like not to miss a thing.
We have Nand, Nor and MRAM connected to LBC.
Since RFS is running from NAND and we use the MRAM as a non-volatile
SRAM I'd like to avoid be
Grant, Anton,
we're about to get new MPC8377 based hardware with various peripherals.
There are two I2C-to-SPI bridge devices (NXP SC18IS602) and I'm not sure
how to define a proper dts...
Of course it's an easy thing creating 2 child nodes on the CPU's I2C
device - but how can I represent the
On 03/25/2011 10:28 AM, Andre Schwarz wrote:
Grant, Anton,
got it.
providing modalis = "spidev" within spi_board_info works like a charme ...
Cheers,
André
we're about to get new MPC8377 based hardware with various
peripherals.
There are two I2C-to-SPI bridge devices (NXP
Matt Sealey wrote:
On Mon, Jan 26, 2009 at 10:34 PM, Grant Likely
wrote:
From: Grant Likely
This patch ensures that memory gets properly mapped into the PCI
address space. Without this patch, the memory window BAR is left
at whatever value happened to be loaded into the BAR when Linux
was
Grzegorz Bernacki wrote:
Grant Likely wrote:
+/dts-v1/;
+
+/ {
+ model = "mtc,digsy";
+ compatible = "mtc,digsy";
This should be something like: "intercontrol,digsy-mtc". Compatible
values should be in the form ",".
ok, I will change it
+ mpc52
Grant Likely wrote:
On Mon, Feb 2, 2009 at 4:58 PM, Wolfgang Denk wrote:
Dear Grzegorz Bernacki,
In message <49872268.10...@semihalf.com> you wrote:
We also had this kind of problem - after feeding some nfs options it
worked :
rsize=8192,wsize=8192,soft,intr,tcp,nolock
it s
Tobias,
are you starting with 2.6.28 or are you upgrading ?
My system runs very fine with 2.6.27
Tobias Knutsson wrote:
I am currently trying to get an MPC5200-based board to run Linux
2.6.28. Most of the devices are working, however i have some issues
with the PCI-bus. More precisely, the
Ira,
we have a pretty old PCI device driver here that needs some basic rework
running on 2.6.27 on several MPC83xx.
It's a simple char-device with "give me some data" implemented using
read() resulting in zero-copy DMA to user mem.
There's get_user_pages() working under the hood along with
S
Ira,
On Mon, May 23, 2011 at 11:12:41AM +0200, Andre Schwarz wrote:
Ira,
we have a pretty old PCI device driver here that needs some basic rework
running on 2.6.27 on several MPC83xx.
It's a simple char-device with "give me some data" implemented using
read() resulting in z
David,
we have a pretty old PCI device driver here that needs some
basic rework running on 2.6.27 on several MPC83xx.
It's a simple char-device with "give me some data" implemented
using read() resulting in zero-copy DMA to user mem.
There's get_user_pages() working under the hood along with
Se
Hi,
I'd like to use a SRAM device (512K*8) connected to a MPC8377 localbus.
What's a decent way to do this (mmap'ed access) running v2.6.34 ?
Is platform RAM (drivers/mtd/maps/plat-ram.c) a good starting point ?
Any hints are welcome.
--
Regards,
Andre
MATRIX VISION GmbH, Talstrasse 16,
Anton,
we're about to get new MPC8377 based hardware with various peripherals.
There are two I2C-to-SPI bridge devices (NXP SC18IS602) and I'm not sure
how to define a proper dts...
Of course it's an easy thing creating 2 child nodes on the CPU's I2C
device - but how can I represent the creat
en SICRL always uses port0:
} else if (prop && !strcmp(prop, "ulpi")) {
sicrl |= MPC834X_SICRL_USB0;
Is this also correct for MPC8343 ? Do we need MPC834X_SICRL_USB1 on 8343 ?
Any help is welcome.
regards,
Andre Schwarz
Matrix Vision
t it a fixed delay regarding to some kind of spec or is it possibly a
spi driver/mmc layer issue ?
regards,
Andre Schwarz
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armi
kunmap(sg_page(&um->sl[i]));
#endif
}
}
regards,
Andre Schwarz
Matrix Vision
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe
Sascha, Grant,
I'm running on 2.6.26-rc6 with an MPC5200B based system.
Looks like some (for me) crucial GPIO are touched during boot.
Is this possible ?
Of course I have compiled in GPIO-Lib and specified the GPIOs in the dts.
But no access yet - I'd like to preserve the setup from u-boot...
r
Grant Likely schrieb:
> On Fri, Jul 04, 2008 at 11:57:14AM +0200, Andre Schwarz wrote:
>
>> Sascha, Grant,
>>
>> I'm running on 2.6.26-rc6 with an MPC5200B based system.
>>
>> Looks like some (for me) crucial GPIO are touched during boot.
>> Is thi
The mvBlueCOUGAR-P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000). It's just another MPC5200_simple board.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
Grant,
I don't know if there are any merge windows ...
If the patch should b
David,
thanks - removed "device_type" from the DMA controller.
Which nodes actually require "device_type" and which don't ?
Is there some general rule ?
regards,
Andre
David Gibson schrieb:
> On Fri, Jul 04, 2008 at 06:35:39PM +0200, Andre Schwarz wrote:
>
The mvBlueCOUGAR-P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000). It's just another MPC5200_simple board.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
Grant,
please find attached the re-submitted patch with mods as you requested
Grant,
do you know if someone's working on a more generic DMA solution using
BestComm engine on 5200B ?
Maybe somthing that accepts a sg-list with callback ops or completion ?
Is it possible right now to accelerate simple memcpy ops ?
regards,
Andre
MATRIX VISION GmbH, Talstraße 16, DE-71570
David Gibson schrieb:
> On Mon, Jul 07, 2008 at 10:14:29AM +0200, Andre Schwarz wrote:
>
>> The mvBlueCOUGAR-P is a MPC5200B based camera system with Intel Gigabit
>> ethernet
>> controller (using e1000). It's just another MPC5200_simple board.
>>
>
The mvBlueCOUGAR-P is a MPC5200B based camera system with Intel Gigabit ethernet
controller (using e1000). It's just another MPC5200_simple board.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
Grant,
I've fixed the dts issues from David (cell-index on gpt).
Please l
as a PCI target since external burst won't be
possible
at all.
Setting the WCT to 0x08 (cache-line size) leads to good overall perfomance.
Signed-off-by: Andre Schwarz <[EMAIL PROTECTED]>
---
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgerich
Grant,
I've pulled the latest git and built a mpc5200_simple system with a
minimal dts.
There's not a single char put on the console
Grant Likely schrieb:
On Sun, Mar 16, 2008 at 1:15 PM, André Schwarz
<[EMAIL PROTECTED]> wrote:
All,
I'm quite stuck in getting our MPC5200B based
nabled
....
regards,
Andre
Andre Schwarz schrieb:
Grant,
I've pulled the latest git and built a mpc5200_simple system with a
minimal dts.
There's not a single char put on the console
Grant Likely schrieb:
On Sun, Mar 16, 2008 at 1:15 PM, André Schwarz
<[EMAIL PROTEC
Grant Likely schrieb:
On Tue, Mar 18, 2008 at 4:34 AM, Andre Schwarz
<[EMAIL PROTECTED]> wrote:
Grant,
sorry for having troubled you. Looks like the build system has been in an
invalid state...
After doing a git-pull and "make distclean" + "make mpc5200_defconfig&q
Grant Likely schrieb:
On Tue, Mar 18, 2008 at 9:14 AM, Andre Schwarz
<[EMAIL PROTECTED]> wrote:
I've read some discussions about the "interrupt-map" attribute of the pci
node. I tried to follow Ben and David in their explanations - obviously I
didn't really get i
i-cache-size = <0x8000>;
timebase-frequency = <0x03f940aa>;
bus-frequency = <0x0fe502a8>;
clock-frequency = <0x17d783fc>;
};
};
Any hints ?
regards,
Andre Schwarz
Matrix Vis
Scott Wood schrieb:
On Sat, Apr 05, 2008 at 10:19:49AM +0200, André Schwarz wrote:
Kernel starts and crashes with "unable to handle kernel paging request @
".
After turning debug on in some files I can see that the initrd memory
gets reserved and the dtb is parsed correctly.
PCI
sorry - forgot Kim + List
Original-Nachricht
Betreff:Re: MPC8343 - "unable to handle paging request @ 0"
Datum: Tue, 08 Apr 2008 13:29:20 +0200
Von:Andre Schwarz <[EMAIL PROTECTED]>
An: Scott Wood <[EMAIL PROTECTED]>
Referenzen: <[E
Scott Wood schrieb:
On Sat, Apr 05, 2008 at 10:19:49AM +0200, André Schwarz wrote:
Kernel starts and crashes with "unable to handle kernel paging request @
".
After turning debug on in some files I can see that the initrd memory
gets reserved and the dtb is parsed correctly.
PCI
Scott Wood schrieb:
On Tue, Apr 08, 2008 at 03:50:26PM +0200, Andre Schwarz wrote:
after building a debug kernel and attaching the bdi2000 it looks like
the crash occurs during "console_init()" ...
Does your device tree have a /chosen node after u-boot is do
Scott Wood schrieb:
Andre Schwarz wrote:
-> find_legacy_serial_port()
stdout is /[EMAIL PROTECTED]/[EMAIL PROTECTED]
It looks like you have some memory corruption between here...
clocksource: timebase mult[3c1] shift[22] registe
Scott Wood schrieb:
Andre Schwarz wrote:
Scott Wood schrieb:
Andre Schwarz wrote:
-> find_legacy_serial_port()
stdout is /[EMAIL PROTECTED]/[EMAIL PROTECTED]
It looks like you have some memory corruption between here...
clocksource: timebase mult[3c1] shift[22] registe
side on
0xFF80 at cs0.
Any hints ?
regards,
Andre Schwarz
Matrix Vision
dts syntax :
[EMAIL PROTECTED] {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8343-localbus", "fsl,pq2pro
Scott,
there has been a "compatible=soc" in my of_bus_id[] ...
It was taken from mpc834x_mds some weeks ago.
I changed to :
static struct of_device_id __initdata of_bus_ids[] = {
{ .compatible = "fsl,pq2pro-localbus", },
{},
};
now it works fine.
Thanks !
Andre
Scott Wood sc
t registered.
usbcore: registered new interface driver libusual
Clocks and communication are looking fine (from an electrical point of
view) and bus power is applied.
But : no device (mouse, memory stick, ...) gets recognized.
No interrupts either.
An hints ?
regards,
Andre Schwarz
Mat
quot; is a PCI Ath5k WiFi module connected to IRQ1, i.e. mapped to
vector 17.
Are the IRQ numbers shifted/mapped/scrambled in any way ?
Can anyone shed some light on this ?
Cheers,
Andre Schwarz
Matrix Vision
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
A
Scott Wood schrieb:
On Tue, Apr 22, 2008 at 06:58:33PM +0200, Andre Schwarz wrote:
I wonder if the IRQ number should match the vector of the datasheet ...
giving :
No. The numbers in /proc/interrupts are virtual IRQ numbers, which are a
purely Linux-internal construct.
-Scott
Scott Wood schrieb:
On Tue, Apr 22, 2008 at 07:36:48PM +0200, Andre Schwarz wrote:
thanks - any Idea how to figure out where the BAD comes from ?
Is it simply an unhandled/unacked one ?
It generally happens when an interrupt is requested, and the core takes
the exception, but then the
e matches with output regarding handler.
Any help is welcome !
regards,
Andre Schwarz
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Amtsgericht Stuttgart, HRB 271090
Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
I can only tell how I do on MPC834x :
Table 8-6. IVEC/CVEC/MVEC Field Definition
Interrupt ID Number Interrupt Meaning
17 IRQ1
18 IRQ2
19 IRQ3
20
Jürgen,
Have a look at the manual chapter 4 (=Reset + Config).
SRESET (issued by gpt0 - watchdog) isn't supposed to do a full hardware
reset.
Looks like you should make use of the SRESET and trigger HRESET accordingly.
I could solve this with _not_ using the internal watchdog but an
external
All,
we're running 2.6.27 on a MPC8343 cpu - nothing special so far.
With heavy system load I get a machine check exception on some boards
within 1-3 days leading to immediate reset.
U-Boot blames "Check Stop" causing the reset - I can also observe the
check_stop_out signal of the CPU being asse
All,
is anybody working on some improvements regarding configurable I2C
frequency inside the i2c-mpc driver ?
If not - would anybody be intersted in getting this done, i.e.
configurable via device tree ?
regards,
Andre
MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht:
Timur Tabi schrieb:
> On Thu, Nov 27, 2008 at 9:00 AM, Andre Schwarz
> <[EMAIL PROTECTED]> wrote:
>
>> All,
>>
>> is anybody working on some improvements regarding configurable I2C
>> frequency inside the i2c-mpc driver ?
>>
>> If not - w
Timur,
is it possible that the PHY adress doesn't match the one specified in
the dts ?
regards,
Andre
Timur Tabi schrieb:
> The Freescale MPC8349e-MITX reference board has two TSECs, the second
> of which (eth1) is attached to a Vitesse 7385 5-port switch.
>
> Using the latest U-Boot, Kernel, an
Timur Tabi schrieb:
> Andre Schwarz wrote:
>
>> Timur,
>>
>> is it possible that the PHY adress doesn't match the one specified in
>> the dts ?
>>
>
> What part of the DTS contains the PHY address? I have this:
>
> [E
Sai Amruta wrote:
Hi All,
I am using linux-2.6.26 on MPC8567 and microSD is connected through
SPI interface.
Is the existing mmc driver supports microSD?
yes - it's working perfectly fine on my MPC8343.
Even with SDHC cards ;-)
cheers,
Andre
--
--Amru
-
Wolfgang Wegner wrote:
Hi Andre,
On Fri, Jan 23, 2009 at 01:43:47PM +0100, Andre Schwarz wrote:
Sai Amruta wrote:
Hi All,
I am using linux-2.6.26 on MPC8567 and microSD is connected through
SPI interface.
Is the existing mmc driver supports microSD?
yes - it's wo
Wolfgang Wegner wrote:
Hi Andre,
On Fri, Jan 23, 2009 at 01:43:47PM +0100, Andre Schwarz wrote:
Sai Amruta wrote:
Hi All,
I am using linux-2.6.26 on MPC8567 and microSD is connected through
SPI interface.
Is the existing mmc driver supports microSD?
yes - it's wo
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