On Thu, 2017-10-19 at 00:02 +1100, Michael Ellerman wrote:
> Breno Leitao writes:
>
> > Currently xmon could call XIVE functions from OPAL even if the XIVE is
> > disabled or does not exist in the system, as in POWER8 machines. This
> > causes the following exception:
> >
> > 1:mon> dx
> > cp
Implement the architecture specific cache maintence functions that make
up the "PMEM API". Currently the writeback and invalidate functions
are the same since the function of the DCBST (data cache block store)
instruction is typically interpreted as "writeback to the point of
coherency" rather than
Implement the architecture specific portitions of the UACCESS_FLUSHCACHE
API. This provides functions for the copy_user_flushcache iterator that
ensure that when the copy is finished the destination buffer contains
a copy of the original and that the destination buffer is clean in the
processor cac
Hi Frank,
> On Oct 19, 2017, at 00:46 , Frank Rowand wrote:
>
> On 10/18/17 11:30, Rob Herring wrote:
>> On Wed, Oct 18, 2017 at 10:53 AM, Pantelis Antoniou
>> wrote:
>>> On Wed, 2017-10-18 at 10:44 -0500, Rob Herring wrote:
On Wed, Oct 18, 2017 at 10:12 AM, Alan Tull wrote:
> On Tue,
Hi Rob,
> On Oct 18, 2017, at 21:30 , Rob Herring wrote:
>
> On Wed, Oct 18, 2017 at 10:53 AM, Pantelis Antoniou
> wrote:
>> On Wed, 2017-10-18 at 10:44 -0500, Rob Herring wrote:
>>> On Wed, Oct 18, 2017 at 10:12 AM, Alan Tull wrote:
On Tue, Oct 17, 2017 at 6:51 PM, Frank Rowand
wr
Hi Michael,
Michael Bringmann writes:
> pseries/findnodes: On pseries systems which allow 'hot-add' of
This isn't a powerpc or pseries patch, so the subject/prefix is wrong.
Also because you're changing generic code you need to provide an
explanation that makes sense in general, across all arch
On 10/12/2017 12:17 PM, Michael Ellerman wrote:
+ pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n");
+ cur_cpu_spec->cpu_features |= CPU_FTR_TM;
+ cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NO_SUSPEND;
+ tm_suspend_disabled = true;
This does
Le 11/10/2017 à 14:30, Vaibhav Jain a écrit :
Presently the PSL9 specific cxl_stop_trace_psl9() only stops the RX0
traces on the CXL adapter when a PSL error irq is triggered. The patch
updates the function to stop all the traces arrays and move them to
the FIN state. The implementation issues
On Thu, Oct 19, 2017 at 2:28 PM, Jerome Glisse wrote:
> On Thu, Oct 19, 2017 at 02:04:26PM +1100, Balbir Singh wrote:
>> On Mon, 16 Oct 2017 23:10:02 -0400
>> jgli...@redhat.com wrote:
>>
>> > From: Jérôme Glisse
>> >
>> > + /*
>> > +* No need to call mmu_notifier_invalidate
On 10/19/2017 03:05 AM, Michael Ellerman wrote:
> [...]
> I know it's annoying when you get stuck with a box like this, but I
> can't merge this patch.
>
> You're *removing* the system administrators ability to control access to
> xmon (other than disabling sysrq entirely). That's a regression.
>
Le 19/10/2017 à 09:13, Oliver O'Halloran a écrit :
Implement the architecture specific cache maintence functions that make
up the "PMEM API". Currently the writeback and invalidate functions
are the same since the function of the DCBST (data cache block store)
instruction is typically interpret
Le 19/10/2017 à 09:13, Oliver O'Halloran a écrit :
Implement the architecture specific portitions of the UACCESS_FLUSHCACHE
API. This provides functions for the copy_user_flushcache iterator that
ensure that when the copy is finished the destination buffer contains
a copy of the original and th
Hello,
On Wed, 18 Oct 2017 21:24:25 +0200
SF Markus Elfring wrote:
> From: Markus Elfring
> Date: Wed, 18 Oct 2017 19:14:39 +0200
>
> The variable "table_group" will be set to an appropriate pointer.
> Thus omit the explicit initialisation at the beginning.
>
> Signed-off-by: Markus Elfring
Hello,
On Wed, 18 Oct 2017 21:26:10 +0200
SF Markus Elfring wrote:
> From: Markus Elfring
> Date: Wed, 18 Oct 2017 20:15:32 +0200
>
> Return directly after a call of the function "kzalloc_node" failed
> at the beginning.
>
> Signed-off-by: Markus Elfring
> ---
> arch/powerpc/platforms/pseri
>> static struct iommu_table_group *iommu_pseries_alloc_group(int node)
>> {
>> -struct iommu_table_group *table_group = NULL;
>> +struct iommu_table_group *table_group;
>> struct iommu_table *tbl = NULL;
>> struct iommu_table_group_link *tgl = NULL;
>>
>
> I think initializi
Hello,
On Mon, 16 Oct 2017 19:34:56 +0200
SF Markus Elfring wrote:
> From: Markus Elfring
> Date: Mon, 16 Oct 2017 19:00:34 +0200
>
> Two pointer checks could be repeated by the tpm_ibmvtpm_probe()
> function during error handling even if the relevant properties can be
> determined for the in
On Wed, 18 Oct 2017 21:03:13 +0300
Andy Shevchenko wrote:
> On Wed, 2017-10-18 at 19:48 +0200, SF Markus Elfring wrote:
> > > For 1/4 and 2/4: explain why the message can be omitted.
>
> > > That's all.
> >
> > I assume that there might be also some communication challenges
> > involved.
>
Florian Weimer writes:
> On 10/12/2017 12:17 PM, Michael Ellerman wrote:
>> +pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n");
>> +cur_cpu_spec->cpu_features |= CPU_FTR_TM;
>> +cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NO_SUSPEND;
>> +tm_suspend_dis
>> @@ -61,7 +61,7 @@ static struct iommu_table_group
>> *iommu_pseries_alloc_group(int node)
>> table_group = kzalloc_node(sizeof(*table_group), GFP_KERNEL,
>> node); if (!table_group)
>> -goto fail_exit;
>> +return NULL;
>>
>> tbl = kzalloc_node(sizeof(*tbl),
On Wed, Oct 18, 2017 at 07:48:06PM +0200, SF Markus Elfring wrote:
> > For 1/4 and 2/4: explain why the message can be omitted.
>
> Why did you not reply directly with this request for the update steps
> with the subject “Delete an error message for a failed memory allocation
> in tpm_…()”?
>
> h
>> @@ -683,13 +683,10 @@ static int tpm_ibmvtpm_probe(struct vio_dev *vio_dev,
>> reg_crq_cleanup:
>> dma_unmap_single(dev, ibmvtpm->crq_dma_handle,
>> CRQ_RES_BUF_SIZE, DMA_BIDIRECTIONAL);
>> -cleanup:
>> -if (ibmvtpm) {
>> -if (crq_q->crq_addr)
>> -free_pa
On Thu, 19 Oct 2017 14:04:43 +0200
SF Markus Elfring wrote:
> >> @@ -61,7 +61,7 @@ static struct iommu_table_group
> >> *iommu_pseries_alloc_group(int node) table_group =
> >> kzalloc_node(sizeof(*table_group), GFP_KERNEL, node); if
> >> (!table_group)
> >> - goto fail_exit;
> >> +
On 10/19/2017 02:04 PM, Tulio Magno Quites Machado Filho wrote:
Florian Weimer writes:
On 10/12/2017 12:17 PM, Michael Ellerman wrote:
+ pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n");
+ cur_cpu_spec->cpu_features |= CPU_FTR_TM;
+ cur_cpu_spec->cpu_use
On Thu, 19 Oct 2017 14:36:09 +0200
SF Markus Elfring wrote:
> >> @@ -683,13 +683,10 @@ static int tpm_ibmvtpm_probe(struct vio_dev
> >> *vio_dev, reg_crq_cleanup:
> >>dma_unmap_single(dev, ibmvtpm->crq_dma_handle,
> >> CRQ_RES_BUF_SIZE, DMA_BIDIRECTIONAL);
> >> -cleanup:
> >> - if (ibmvtpm)
On Thu, Oct 19, 2017 at 01:37:18PM +0200, Michal Suchánek wrote:
> Hello,
>
> On Wed, 18 Oct 2017 21:24:25 +0200
> SF Markus Elfring wrote:
>
> > From: Markus Elfring
> > Date: Wed, 18 Oct 2017 19:14:39 +0200
> >
> > The variable "table_group" will be set to an appropriate pointer.
> > Thus om
On Wed, 2017-10-18 at 14:18 +1100, Michael Ellerman wrote:
> Mimi Zohar writes:
> > On Tue, 2017-10-17 at 12:11 +0200, Julia Lawall wrote:
> >> On Tue, 17 Oct 2017, Dan Carpenter wrote:
> >> > On Tue, Oct 17, 2017 at 10:56:42AM +0200, Julia Lawall wrote:
> >> > > On Tue, 17 Oct 2017, Dan Carpenter
On 10/19/2017 09:10 AM, Benjamin Herrenschmidt wrote:
> On Thu, 2017-10-19 at 00:02 +1100, Michael Ellerman wrote:
>> Breno Leitao writes:
>>
>>> Currently xmon could call XIVE functions from OPAL even if the XIVE is
>>> disabled or does not exist in the system, as in POWER8 machines. This
>>> ca
Forwarding some comments from Adhemerval sent to libc-alpha [1]...
Adhemerval Zanella writes:
>Florian Weimer writes:
>
>> On 10/12/2017 12:17 PM, Michael Ellerman wrote:
>>> + pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n");
>>> + cur_cpu_spec->cpu_features |= CPU_FTR_
On Thu, Oct 19, 2017 at 01:56:32PM +0200, Michal Suchánek wrote:
>
> I think a single cleanup section is better than many labels that just
> avoid a single null check.
>
I am not a big advocate of churn, but one err style error handling is
really bug prone.
I'm dealing with static analysis so mo
On Thu, 19 Oct 2017 15:55:59 +0300
Dan Carpenter wrote:
> On Thu, Oct 19, 2017 at 01:37:18PM +0200, Michal Suchánek wrote:
> > Hello,
> >
> > On Wed, 18 Oct 2017 21:24:25 +0200
> > SF Markus Elfring wrote:
> >
> > > From: Markus Elfring
> > > Date: Wed, 18 Oct 2017 19:14:39 +0200
> > >
> >
Hello,
Michael, sorry for the delay. I'm catching up with the emails
after... absence.
On (10/04/17 22:06), Michael Ellerman wrote:
> Petr Mladek writes:
> > On Sat 2017-09-30 11:53:16, Sergey Senozhatsky wrote:
> >> diff --git a/arch/powerpc/kernel/module_64.c
> >> b/arch/powerpc/kernel/module
Michael,
On (09/27/17 15:01), Michael Ellerman wrote:
> Sergey Senozhatsky writes:
>
> > On (09/22/17 16:48), Luck, Tony wrote:
> > [..]
> >> Tested patch series on ia64 successfully.
> >>
> >> Tested-by: Tony Luck
> >
> > thanks!
> >
> >> After this goes upstream, you should submit a patch to
On Thu, 19 Oct 2017 16:36:46 +0300
Dan Carpenter wrote:
> On Thu, Oct 19, 2017 at 01:56:32PM +0200, Michal Suchánek wrote:
> >
> > I think a single cleanup section is better than many labels that
> > just avoid a single null check.
> >
>
> I am not a big advocate of churn, but one err style e
tpm_ibmvtpm_probe() is an example of poor names. It has the generic
ones like "cleanup" which don't say *what* is cleaned and the come-from
ones like "init_irq_cleanup" which don't say anything useful at all:
647 rc = request_irq(vio_dev->irq, ibmvtpm_interrupt, 0,
648
On Thu, Oct 19, 2017 at 04:16:37PM +0200, Michal Suchánek wrote:
> On Thu, 19 Oct 2017 16:36:46 +0300
> Dan Carpenter wrote:
>
> > On Thu, Oct 19, 2017 at 01:56:32PM +0200, Michal Suchánek wrote:
> > >
> > > I think a single cleanup section is better than many labels that
> > > just avoid a sing
On Mon, Oct 16, 2017 at 02:44:42PM +0200, Christoph Hellwig wrote:
> On Tue, Oct 03, 2017 at 12:49:51PM +0100, Robin Murphy wrote:
> > Reviewed-by: Robin Murphy
>
> Thanks Robin. I've heard very little from the arch maintainers,
> but if people remain silent I will apply the whole series to the
On 19/10/2017 11:34, Tulio Magno Quites Machado Filho wrote:
> Forwarding some comments from Adhemerval sent to libc-alpha [1]...
>
> Adhemerval Zanella writes:
>> Florian Weimer writes:
>>
>>> On 10/12/2017 12:17 PM, Michael Ellerman wrote:
+ pr_info("Enabling TM (Transactional Memory)
On Thu, 2017-10-19 at 15:09 +0200, Cédric Le Goater wrote:
> > No that's wrong. xive_enabled() is only set if Linux is using native
> > xive mode but some of those xmon functions dump the emulated state.
> >
> > We should fix the actual cause of the crash.
>
> which should be in the OPAL XIVE dum
On Thu, Oct 19, 2017 at 10:02:13AM +1100, Balbir Singh wrote:
> On Wed, 18 Oct 2017 13:57:39 -0700
> Ram Pai wrote:
>
> > On Wed, Oct 18, 2017 at 03:15:22PM +1100, Balbir Singh wrote:
> > > On Fri, 8 Sep 2017 15:44:59 -0700
> > > Ram Pai wrote:
> > >
> > > > This patch provides the implement
>>> The "Fixes" tag is an indication that the patch should be backported.
>>
>> No it's not that strong. It's an indication that the patch fixes another
>> commit, which may or may not mean it should be backported depending on
>> the preferences of the backporter. If it *does* need backporting then
On Thu, Oct 19, 2017 at 10:04:40AM +1100, Balbir Singh wrote:
> On Wed, 18 Oct 2017 14:10:41 -0700
> Ram Pai wrote:
>
> > On Wed, Oct 18, 2017 at 03:36:35PM +1100, Balbir Singh wrote:
> > > On Fri, 8 Sep 2017 15:45:01 -0700
> > > Ram Pai wrote:
> > >
> > > > arch independent code calls arch_
On Thu, Oct 19, 2017 at 10:08:57AM +1100, Balbir Singh wrote:
> On Wed, 18 Oct 2017 14:29:24 -0700
> Ram Pai wrote:
>
> > On Thu, Oct 19, 2017 at 06:57:32AM +1100, Balbir Singh wrote:
> > > On Fri, 8 Sep 2017 15:45:06 -0700
> > > Ram Pai wrote:
> > >
> > > > Make sure that the kernel does no
On Thu, Oct 19, 2017 at 10:27:52AM +1100, Balbir Singh wrote:
> On Fri, 8 Sep 2017 15:45:08 -0700
> Ram Pai wrote:
>
> > Handle Data and Instruction exceptions caused by memory
> > protection-key.
> >
> > The CPU will detect the key fault if the HPTE is already
> > programmed with the key.
> >
On Thu, Oct 19, 2017 at 10:29:44AM +1100, Balbir Singh wrote:
> On Fri, 8 Sep 2017 15:45:09 -0700
> Ram Pai wrote:
>
> > get_pte_pkey() helper returns the pkey associated with
> > a address corresponding to a given mm_struct.
> >
>
> This is really get_mm_addr_key() -- no?
ok. will be so.
RP
On Thu, Oct 19, 2017 at 09:53:11PM +1100, Balbir Singh wrote:
> On Thu, Oct 19, 2017 at 2:28 PM, Jerome Glisse wrote:
> > On Thu, Oct 19, 2017 at 02:04:26PM +1100, Balbir Singh wrote:
> >> On Mon, 16 Oct 2017 23:10:02 -0400
> >> jgli...@redhat.com wrote:
> >>
> >> > From: Jérôme Glisse
> >> >
> >
> On Tue, Oct 17, 2017 at 11:50:05AM +, alexander.stef...@infineon.com
> wrote:
> > > > Replace the specification of data structures by pointer dereferences
> > > > as the parameter for the operator "sizeof" to make the corresponding
> > > > size
> > > > determination a bit safer according to t
On Thu, Oct 19, 2017 at 02:25:47PM +1100, Michael Ellerman wrote:
> Ram Pai writes:
>
> > diff --git a/arch/powerpc/mm/hash64_64k.c b/arch/powerpc/mm/hash64_64k.c
> > index 1a68cb1..c6c5559 100644
> > --- a/arch/powerpc/mm/hash64_64k.c
> > +++ b/arch/powerpc/mm/hash64_64k.c
> > @@ -126,18 +113,13
On Thu, Oct 19, 2017 at 03:20:36PM +1100, Michael Ellerman wrote:
> Ram Pai writes:
>
> > diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> > index 9fc3c0b..a4cd210 100644
> > --- a/arch/powerpc/Kconfig
> > +++ b/arch/powerpc/Kconfig
> > @@ -864,6 +864,22 @@ config SECCOMP
> >
> >
When setting nr_cpus=1, we observed a crash in IMC code during boot
due to a missing allocation: basically, IMC code is taking the number
of threads into account in imc_mem_init() and if we manually set
nr_cpus for a value that is not multiple of the number of threads per
core, an integer division
Ping...
Anybody, see any issues with this patch?
-Tyrel
On 09/28/2017 05:19 PM, Tyrel Datwyler wrote:
When a vdevice is DLPAR removed from the system the vio subsystem doesn't
bother unmapping the virq from the irq_domain. As a result we have a virq
mapped to a hardware irq that is no longer v
>> If the code doing the allocation is changed in the future the single
>> cleanup can stay whereas multiple labels have to be rewritten again.
>
> No, they don't unless you choose bad label names. Perhaps numbered
> labels? We don't get a lot of those in the kernel any more. Label
> name shoul
On 10/19/17 13:06, Moritz Fischer wrote:
< snip >
> We also have plenty of code that is just not aware of overlays, and
> assumes certain parts of the tree to stay static.
I would state that somewhat differently. :-) There is very little
code that is aware of overlays, and most code assumes th
On Fri, 13 Oct 2017 13:32:12 -0400 Pavel Tatashin
wrote:
> vmemmap_alloc_block() will no longer zero the block, so zero memory
> at its call sites for everything except struct pages. Struct page memory
> is zero'd by struct page initialization.
>
> Replace allocators in sprase-vmemmap to use t
This looks good to me, thank you Andrew.
Pavel
On Thu, Oct 19, 2017 at 03:55:59PM +0300, Dan Carpenter wrote:
> On Thu, Oct 19, 2017 at 01:37:18PM +0200, Michal Suchánek wrote:
> > Hello,
> >
> > On Wed, 18 Oct 2017 21:24:25 +0200
> > SF Markus Elfring wrote:
> >
> > > From: Markus Elfring
> > > Date: Wed, 18 Oct 2017 19:14:39 +0200
> > >
On Thu, Oct 19, 2017 at 11:51:40AM +0300, Pantelis Antoniou wrote:
> Hi Rob,
>
> > On Oct 18, 2017, at 21:30 , Rob Herring wrote:
> >
> > On Wed, Oct 18, 2017 at 10:53 AM, Pantelis Antoniou
> > wrote:
> >> On Wed, 2017-10-18 at 10:44 -0500, Rob Herring wrote:
> >>> On Wed, Oct 18, 2017 at 10:12
On Thu, 2017-10-19 at 11:34 -0200, Tulio Magno Quites Machado Filho wrote:
> Forwarding some comments from Adhemerval sent to libc-alpha [1]...
>
> Adhemerval Zanella writes:
> > Florian Weimer writes:
> >
> > > On 10/12/2017 12:17 PM, Michael Ellerman wrote:
> > > > + pr_info("Enabling T
On Thu, Oct 19, 2017 at 10:13 PM, Christophe LEROY
wrote:
>
>
> Le 19/10/2017 à 09:13, Oliver O'Halloran a écrit :
>>
>> Implement the architecture specific cache maintence functions that make
>> up the "PMEM API". Currently the writeback and invalidate functions
>> are the same since the function
On Thu, Oct 19, 2017 at 10:14 PM, Christophe LEROY
wrote:
>
>
> Le 19/10/2017 à 09:13, Oliver O'Halloran a écrit :
>>
>> Implement the architecture specific portitions of the UACCESS_FLUSHCACHE
>> API. This provides functions for the copy_user_flushcache iterator that
>> ensure that when the copy
Nicholas Piggin (2):
powerpc: add POWER9_DD20 feature
powerpc/64s: idle skip POWER9 DD1 and DD2.0 specific workarounds on
DD2.1
arch/powerpc/include/asm/cputable.h | 5 -
arch/powerpc/kernel/cputable.c | 20 +++
arch/powerpc/kernel/dt_cpu_ftrs.c | 2 ++
arch/p
Cc: Michael Neuling
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/cputable.h | 5 -
arch/powerpc/kernel/cputable.c | 20
arch/powerpc/kernel/dt_cpu_ftrs.c | 2 ++
3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/a
DD2.1 does not have to flush the ERAT after a state-loss idle. It also
does not have to save and restore MMCR0.
Performance testing was done on a DD2.1 using only the stop0 idle state
(the shallowest state which supports state loss), using context_switch
selftest configured to ping-poing between t
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