On Mon, Jul 24, 2017 at 02:24:14AM +, Qiang Zhao wrote:
> On Sat 7/22/2017 3:34 PM, Dan Carpenter wrote:
>
> > -Original Message-
> > From: Dan Carpenter [mailto:dan.carpen...@oracle.com]
> > Sent: Saturday, July 22, 2017 3:34 PM
> > To: Qiang Zhao
> > Cc: Leo Li ; linuxppc-dev@lists
It would be nice to be able to dump page tables in a
particular context.
Example use cases
Dumping PTE contents to see the keys (useful for debugging)
0:mon> dv 0x77f7 c0003b585080
PGD@0xc0003ab651f8->0x3a255800
PUD@0xc0003a255bf8->0x3aa84000
PMD@0xc0003aa
We don't support allocating them runtime. Only supported mechanism as of now is
HMC based hypervisor interface. So disable 16G hugetlb on powernv platform
Signed-off-by: Aneesh Kumar K.V
---
May be this should go to -stable ?. To show the 16G pagesize in
/sys/kernel/mm/hugepages/ confuse users
Hi Matt,
On Mon, Jul 24, 2017 at 11:01:06AM +1000, Matt Brown wrote:
> + for (i = 0; i < (64 / size); i++) {
If you do
for (i = 0; i < 64; i += size)
things are slightly nicer.
> + if ((i * size) < 32)
> + low |= n << (i * size);
> + else
> +
On 23/06/17 18:47, Ivan Mikhaylov wrote:
> * shdci-st driver can be used for ppc476 fsp2 soc
shdci-st -> sdhci-st
>
> Signed-off-by: Ivan Mikhaylov
Acked-by: Adrian Hunter
> ---
> drivers/mmc/host/Kconfig |2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/driver
Michael Ellerman writes:
> "Aneesh Kumar K.V" writes:
>
>> On Wednesday 28 June 2017 12:48 PM, Alexey Kardashevskiy wrote:
>>> On 28/06/17 16:09, Aneesh Kumar K.V wrote:
We can use pfn_to_page in realmode for other configs. Hence remove the
CONFIG_FLATMEM ifdef
>>>
>>> For CONFIG_SPAR
On Mon 7/24/2017 3:04 PM, Dan Carpenter
> -Original Message-
> From: Dan Carpenter [mailto:dan.carpen...@oracle.com]
> Sent: Monday, July 24, 2017 3:04 PM
> To: Qiang Zhao
> Cc: Leo Li ; linuxppc-dev@lists.ozlabs.org; kernel-
> janit...@vger.kernel.org
> Subject: Re: [PATCH 1/2] fsl/qe:
On Mon, Jul 24, 2017 at 09:39:32AM +, Qiang Zhao wrote:
> On Mon 7/24/2017 3:04 PM, Dan Carpenter
>
> > -Original Message-
> > From: Dan Carpenter [mailto:dan.carpen...@oracle.com]
> > Sent: Monday, July 24, 2017 3:04 PM
> > To: Qiang Zhao
> > Cc: Leo Li ; linuxppc-dev@lists.ozlabs.o
"Aneesh Kumar K.V" writes:
> We don't support allocating them runtime. Only supported mechanism as of now
> is
> HMC based hypervisor interface. So disable 16G hugetlb on powernv platform
>
> Signed-off-by: Aneesh Kumar K.V
> ---
>
> May be this should go to -stable ?. To show the 16G pagesize
On Mon, Jul 24, 2017 at 11:01 AM, Matt Brown
wrote:
> This adds emulations for the popcntb, popcntw, and popcntd instructions.
> Tested for correctness against the popcnt{b,w,d} instructions on ppc64le.
>
> Signed-off-by: Matt Brown
> ---
> v2:
> - fixed opcodes
> - fixed typecast
Hi,
next-20170721 on powerpc triggered kernel panic for stress test.
Machine : Power 8 Bare-metal
Kernel : 4.13.0-rc1-next-20170721
gcc : 4.8.5
config: Tul-NV-config attached
Is reproducible all the time ? : No
Test:
stress --cpu 160 --io 160 --vm 160 --vm-bytes 261536768 --hdd 160
--hdd-bytes 1
Laurent Vivier writes:
> As for commit 68baf692c435 ("powerpc/pseries: Fix of_node_put()
> underflow during DLPAR remove"), the call to of_node_put()
> must be removed from pSeries_reconfig_remove_node().
>
> dlpar_detach_node() and pSeries_reconfig_remove_node() call
> of_detach_node(), and thus
LEROY Christophe writes:
> Benjamin Herrenschmidt a écrit :
>
>> When hitting below a VM_GROWSDOWN vma (typically growing the stack),
>> we check whether it's a valid stack-growing instruction and we
>> check the distance to GPR1. This is largely open coded with lots
>> of comments, so move it o
On Mon, 24 Jul 2017 14:28:00 +1000
Benjamin Herrenschmidt wrote:
> There is no guarantee that the various isync's involved with
> the context switch will order the update of the CPU mask with
> the first TLB entry for the new context being loaded by the HW.
>
> Be safe here and add a memory barr
On Mon, 24 Jul 2017 14:28:02 +1000
Benjamin Herrenschmidt wrote:
> Instead of comparing the whole CPU mask every time, let's
> keep a counter of how many bits are set in the mask. Thus
> testing for a local mm only requires testing if that counter
> is 1 and the current CPU bit is set in the mask
LEROY Christophe writes:
> Benjamin Herrenschmidt a écrit :
>
>> Define a common page_fault_is_write() helper and use it
>>
>> Signed-off-by: Benjamin Herrenschmidt
>> ---
>> arch/powerpc/mm/fault.c | 18 +++---
>> 1 file changed, 11 insertions(+), 7 deletions(-)
>>
>> diff --git a
Although pretty much everyone using powernv is running little endian,
we should still test we can build for big endian. So add a
powernv_be_defconfig, which is autogenerated by flipping the endian
symbol in powernv_defconfig.
Signed-off-by: Michael Ellerman
---
arch/powerpc/Makefile | 4
Nicholas Piggin writes:
> On Mon, 24 Jul 2017 14:28:02 +1000
> Benjamin Herrenschmidt wrote:
>
>> Instead of comparing the whole CPU mask every time, let's
>> keep a counter of how many bits are set in the mask. Thus
>> testing for a local mm only requires testing if that counter
>> is 1 and the
LEROY Christophe writes:
> Benjamin Herrenschmidt a écrit :
>> diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
>> index faddc87d0205..f04bc9f6b134 100644
>> --- a/arch/powerpc/mm/fault.c
>> +++ b/arch/powerpc/mm/fault.c
>> @@ -203,23 +203,13 @@ static int __do_page_fault(struct pt_
For debugging very early boot problems we have CONFIG_PPC_EARLY_DEBUG,
which allows configuring the kernel such that it unconditionally writes
to a particular type of console, regardless of whether that console
exists or not. This is useful sometimes when the kernel crashes before
it can even deter
On Fri, Jul 21, 2017 at 10:01:42PM -0700, Haren Myneni wrote:
>
> This patch adds P9 NX support for 842 compression engine. Virtual
> Accelerator Switchboard (VAS) is used to access 842 engine on P9.
>
> For each NX engine per chip, setup receive window using
> vas_rx_win_open() which configures
Michael Ellerman a écrit :
LEROY Christophe writes:
Benjamin Herrenschmidt a écrit :
When hitting below a VM_GROWSDOWN vma (typically growing the stack),
we check whether it's a valid stack-growing instruction and we
check the distance to GPR1. This is largely open coded with lots
of comm
On 07/24/2017 03:42 AM, Michael Ellerman wrote:
> Laurent Vivier writes:
>
>> As for commit 68baf692c435 ("powerpc/pseries: Fix of_node_put()
>> underflow during DLPAR remove"), the call to of_node_put()
>> must be removed from pSeries_reconfig_remove_node().
>>
>> dlpar_detach_node() and pSeries
On Mon, 2017-07-24 at 21:20 +1000, Nicholas Piggin wrote:
> I think this is the right thing to do, but it should be commented.
> Is hwsync the right barrier? (i.e., it will order the page table walk)
This is an open question, I've asked the architects and HW guys and
waiting for an answer.
That s
On Mon, 2017-07-24 at 21:25 +1000, Nicholas Piggin wrote:
> > +#ifdef CONFIG_PPC_BOOK3S_64
> > +static inline void inc_mm_active_cpus(struct mm_struct *mm)
> > +{
> > + atomic_inc(&mm->context.active_cpus);
> > +}
> > +#else
> > +static inline void inc_mm_active_cpus(struct mm_struct *mm) { }
>
This part of Secure Encrypted Virtualization (SEV) series focuses on the
changes required in a guest OS for SEV support.
When SEV is active, the memory content of guest OS will be transparently
encrypted
with a key unique to the guest VM.
SEV guests have concept of private and shared memory. Pri
Update amd-memory-encryption document describing the AMD Secure Encrypted
Virtualization (SEV) feature.
Signed-off-by: Brijesh Singh
---
Documentation/x86/amd-memory-encryption.txt | 29 ++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/Documentation/x8
From: Tom Lendacky
Update the CPU features to include identifying and reporting on the
Secure Encrypted Virtualization (SEV) feature. SME is identified by
CPUID 0x801f, but requires BIOS support to enable it (set bit 23 of
MSR_K8_SYSCFG and set bit 0 of MSR_K7_HWCR). Only show the SEV featu
From: Tom Lendacky
Provide support for Secure Encyrpted Virtualization (SEV). This initial
support defines a flag that is used by the kernel to determine if it is
running with SEV active.
Signed-off-by: Tom Lendacky
Signed-off-by: Brijesh Singh
---
arch/x86/include/asm/mem_encrypt.h | 2 ++
a
From: Tom Lendacky
When SEV is active the initrd/initramfs will already have already been
placed in memory encyrpted so do not try to encrypt it.
Signed-off-by: Tom Lendacky
Signed-off-by: Brijesh Singh
---
arch/x86/kernel/setup.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
d
From: Tom Lendacky
When SEV is active the trampoline area will need to be in encrypted
memory so only mark the area decrypted if SME is active.
Signed-off-by: Tom Lendacky
Signed-off-by: Brijesh Singh
---
arch/x86/realmode/init.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
di
From: Tom Lendacky
When Secure Encrypted Virtualization (SEV) is active, boot data (such as
EFI related data, setup data) is encrypted and needs to be accessed as
such when mapped. Update the architecture override in early_memremap to
keep the encryption attribute when mapping this data.
Signed-
From: Tom Lendacky
The current code checks only for sme_active() when determining whether
to perform the encryption attribute change. Include sev_active() in this
check so that memory attribute changes can occur under SME and SEV.
Signed-off-by: Tom Lendacky
Signed-off-by: Brijesh Singh
---
From: Tom Lendacky
EFI data is encrypted when the kernel is run under SEV. Update the
page table references to be sure the EFI memory areas are accessed
encrypted.
Signed-off-by: Tom Lendacky
Signed-off-by: Brijesh Singh
---
arch/x86/platform/efi/efi_64.c | 15 ++-
1 file changed,
From: Tom Lendacky
The walk_iomem_res_desc(), walk_system_ram_res() and walk_system_ram_range()
functions each have much of the same code. Create a new function that
consolidates the common code from these functions in one place to reduce
the amount of duplicated code.
Signed-off-by: Tom Lendac
From: Tom Lendacky
In prep for a new function that will need additional resource information
during the resource walk, update the resource walk callback to pass the
resource structure. Since the current callback start and end arguments
are pulled from the resource structure, the callback functio
From: Tom Lendacky
In order for memory pages to be properly mapped when SEV is active, we
need to use the PAGE_KERNEL protection attribute as the base protection.
This will insure that memory mapping of, e.g. ACPI tables, receives the
proper mapping attributes.
Signed-off-by: Tom Lendacky
Signe
From: Tom Lendacky
DMA access to memory mapped as encrypted while SEV is active can not be
encrypted during device write or decrypted during device read. In order
for DMA to properly work when SEV is active, the SWIOTLB bounce buffers
must be used.
Signed-off-by: Tom Lendacky
Signed-off-by: Bri
From: Tom Lendacky
Secure Encrypted Virtualization (SEV) does not support string I/O, so
unroll the string I/O operation into a loop operating on one element at
a time.
Signed-off-by: Tom Lendacky
Signed-off-by: Brijesh Singh
---
arch/x86/include/asm/io.h | 26 ++
1 fi
From: Tom Lendacky
Early in the boot process, add checks to determine if the kernel is
running with Secure Encrypted Virtualization (SEV) active.
Checking for SEV requires checking that the kernel is running under a
hypervisor (CPUID 0x0001, bit 31), that the SEV feature is available
(CPUID
Some KVM-specific custom MSRs shares the guest physical address with
hypervisor. When SEV is active, the shared physical address must be mapped
with encryption attribute cleared so that both hypervsior and guest can
access the data.
Add APIs to change memory encryption attribute in early boot code
Some KVM specific MSR's (steal-time, asyncpf, avic_eio) allocates per-CPU
variable at compile time and share its physical address with hypervisor.
It presents a challege when SEV is active in guest OS, when SEV is active,
the guest memory is encrypted with guest key hence hypervisor will not
able t
The guest physical memory area holding the struct pvclock_wall_clock and
struct pvclock_vcpu_time_info are shared with the hypervisor. Hypervisor
periodically updates the contents of the memory. When SEV is active, we
must clear the encryption attributes from the shared memory pages so that
both hy
Implemented default hugepage size verification (default_hugepagesz=)
in order to allow allocation of defined number of pages (hugepages=)
only for supported hugepage sizes.
Signed-off-by: Victor Aoqui
---
v2:
- Renamed default_hugepage_setup_sz function to hugetlb_default_size_setup;
- Added pow
On Mon, 24 Jul 2017 23:46:44 +1000
Michael Ellerman wrote:
> Nicholas Piggin writes:
>
> > On Mon, 24 Jul 2017 14:28:02 +1000
> > Benjamin Herrenschmidt wrote:
> >
> >> Instead of comparing the whole CPU mask every time, let's
> >> keep a counter of how many bits are set in the mask. Thus
>
On Tue, 25 Jul 2017 06:58:46 +1000
Benjamin Herrenschmidt wrote:
> On Mon, 2017-07-24 at 21:25 +1000, Nicholas Piggin wrote:
> > > +#ifdef CONFIG_PPC_BOOK3S_64
> > > +static inline void inc_mm_active_cpus(struct mm_struct *mm)
> > > +{
> > > + atomic_inc(&mm->context.active_cpus);
> > > +}
>
On Mon, Jul 24, 2017 at 8:28 PM, Balbir Singh wrote:
> On Mon, Jul 24, 2017 at 11:01 AM, Matt Brown
> wrote:
>> This adds emulations for the popcntb, popcntw, and popcntd instructions.
>> Tested for correctness against the popcnt{b,w,d} instructions on ppc64le.
>>
>> Signed-off-by: Matt Brown
>>
On Tue, 2017-07-25 at 10:44 +1000, Nicholas Piggin wrote:
> The two variants are just cleaner versions of the two variants you
> already introduced.
>
> static inline bool mm_activate_cpu(struct mm_struct *mm)
> {
> if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(next))) {
> cpuma
This patch adds emulation of the cmpb instruction, enabling xmon to
emulate this instruction.
Tested for correctness against the cmpb asm instruction on ppc64le.
Signed-off-by: Matt Brown
---
v2:
- fixed opcode
- fixed mask typecasting
---
arch/powerpc/lib/sstep.c | 20 +
This adds emulations for the popcntb, popcntw, and popcntd instructions.
Tested for correctness against the popcnt{b,w,d} instructions on ppc64le.
Signed-off-by: Matt Brown
---
v3:
- optimised using the Giles-Miller method of side-ways addition
v2:
- fixed opcodes
- fixed
This adds emulation for the bpermd instruction.
Tested for correctness against the bpermd instruction on ppc64le.
Signed-off-by: Matt Brown
---
v2:
- fixed opcode
- added ifdef tags to do_bpermd func
- fixed bitshifting errors
---
arch/powerpc/lib/sstep.c | 24 +++
This adds emulation for the prtyw and prtyd instructions.
Tested for logical correctness against the prtyw and prtyd instructions
on ppc64le.
Signed-off-by: Matt Brown
---
v3:
- optimised using the Giles-Miller method of side-ways addition
v2:
- fixed opcodes
- fixed bitsh
This adds emulation for the isel instruction.
Tested for correctness against the isel instruction and its extended
mnemonics (lt, gt, eq) on ppc64le.
Signed-off-by: Matt Brown
---
v2:
- fixed opcode
- fixed definition to include the 'if RA=0, a=0' clause
- fixed ccr bitshi
Tyrel Datwyler writes:
> On 07/24/2017 03:42 AM, Michael Ellerman wrote:
>> Laurent Vivier writes:
>>
>>> As for commit 68baf692c435 ("powerpc/pseries: Fix of_node_put()
>>> underflow during DLPAR remove"), the call to of_node_put()
>>> must be removed from pSeries_reconfig_remove_node().
>>>
>
On 07/24/2017 03:58 PM, Michael Ellerman wrote:
"Aneesh Kumar K.V" writes:
We don't support allocating them runtime. Only supported mechanism as of now is
HMC based hypervisor interface. So disable 16G hugetlb on powernv platform
Signed-off-by: Aneesh Kumar K.V
---
May be this should go t
On Fri, 2017-06-30 at 17:28 +1000, Nicholas Piggin wrote:
> On Fri, 30 Jun 2017 10:52:18 +0530
> Abdul Haleem wrote:
>
> > On Fri, 2017-06-30 at 00:45 +1000, Nicholas Piggin wrote:
> > > On Thu, 29 Jun 2017 20:23:05 +1000
> > > Nicholas Piggin wrote:
> > >
> > > > On Thu, 29 Jun 2017 19:36:14 +
Commit 20dd4c624d251 ('powerpc/perf: Fix SDAR_MODE value for continous
sampling on Power9') set the default sdar_mode value in MMCRA[SDAR_MODE]
to be used as 0b01 (Update on TLB miss). And this value is set if sdar_mode
from event is zero, or we are in continous sampling mode in power9 dd1.
But it
On Mon, Jul 24, 2017 at 02:07:41PM -0500, Brijesh Singh wrote:
Subject: Re: [RFC Part1 PATCH v3 01/17] Documentation/x86: Add AMD Secure
Encrypted Virtualization (SEV) descrption
^^
Current vDSO64 implementation does not have support for coarse clocks
(CLOCK_MONOTONIC_COARSE, CLOCK_REALTIME_COARSE), for which it falls back
to system call, increasing the response time, vDSO implementation reduces
the cycle time. Below is a benchmark of the difference in execution time
with and
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