On Thu, Feb 18, 2016 at 01:39:52PM +1100, Alexey Kardashevskiy wrote:
>
> The latest powerkvm kernel passes @thp instead of NULL and check for it
> below in addition to (shift > PAGE_SHIFT), should it be fixed here as well?
>
> Is that possible for __find_linux_pte_or_hugepte() return thp==true b
Move the logic to work out the kernel toc pointer into a header. This is
a good cleanup, and also means we can use it elsewhere in future.
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/asm/sections.h | 12
arch/powerpc/kernel/paca.c | 11 +--
2 files chan
Currently we generate the module stub for ftrace_caller() at the bottom
of apply_relocate_add(). However apply_relocate_add() is potentially
called more than once per module, which means we will try to generate
the ftrace_caller() stub multiple times.
Although the current code deals with that corr
When a module is loaded, calls out to the kernel go via a stub which is
generated at runtime. One of these stubs is used to call _mcount(),
which is the default target of tracing calls generated by the compiler
with -pg.
If dynamic ftrace is enabled (which it typically is), another stub is
used to
In order to support the new -mprofile-kernel ABI, we need to be able to
call from the module back to ftrace_caller() (in the kernel) without
using the module's r2. That is because the function in this module which
is calling ftrace_caller() may not have setup r2, if it doesn't
otherwise need it (ie
From: Torsten Duwe
Convert powerpc's arch_ftrace_update_code() from its own version to use
the generic default functionality (without stop_machine -- our
instructions are properly aligned and the replacements atomic).
With this we gain error checking and the much-needed function_trace_op
handlin
From: Torsten Duwe
Rather than open-coding -pg whereever we want to disable ftrace, use the
existing $(CC_FLAGS_FTRACE) variable.
This has the advantage that it will work in future when we use a
different set of flags to enable ftrace.
Signed-off-by: Torsten Duwe
Signed-off-by: Michael Ellerma
From: Torsten Duwe
The gcc switch -mprofile-kernel defines a new ABI for calling _mcount()
very early in the function with minimal overhead.
Although mprofile-kernel has been available since GCC 3.4, there were
bugs which were only fixed recently. Currently it is known to work in
GCC 4.9, 5 and
From: Torsten Duwe
Firstly we add logic to Kconfig to allow a user to choose if they want
mprofile-kernel. This has to be user-selectable because only some
current toolchains support it. If we enabled it unconditionally we would
prevent some users from building the kernel entirely.
Arguably it w
On Friday 26 February 2016 18:41:06 Li Yang wrote:
> >> >
> >> > It would be perfect if this it true. But I tried with the following
> >> > change, it just makes QORIQ_CPUFREQ non-selectable if THERMAL=m.
> >> >
> >> > diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
> >> > index dcb
LTO can cause GCC to inline some functions which have attributes set. The
act of inlining the functions can lead to GCC forgetting about the
attributes which leads to incorrect tests.
Notable example being: __attribute__((__target__("no-vsx")))
LTO can also interact strangely with custom assembly f
Hi,
On 25 February 2016 at 11:57, Alessio Igor Bogani
wrote:
> Signed-off-by: Alessio Igor Bogani
> ---
> arch/powerpc/boot/dts/fsl/gef_ppc9a.dts| 284 +++---
> arch/powerpc/boot/dts/fsl/gef_sbc310.dts | 276 +++--
> arch/powerpc/boot/dts/fsl/gef_sb
On Wed, 2016-24-02 at 17:27:51 UTC, Frederic Barrat wrote:
> The PSL timebase synchronization is seemingly failing for
> configuration not including VIRT_CPU_ACCOUNTING_NATIVE. The driver
> shows the following trace in dmesg:
> PSL: Timebase sync: giving up!
>
> The PSL timebase register is actual
On Wed, 2016-24-02 at 01:55:03 UTC, Jeremy Kerr wrote:
> This change adds a defconfig for the non-virtualised power platforms,
> based on pseries_defconfig, but without pseries, and little-endian,
> and no OF trampoline.
>
> Signed-off-by: Jeremy Kerr
> Acked-by: Joel Stanley
Series applied to
On Mon, 2016-22-02 at 02:41:12 UTC, Paul Mackerras wrote:
> From: Paul Mackerras
>
> No code changes.
>
> Signed-off-by: Paul Mackerras
Series applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/1ec3f937102154b54c3ba97b79
cheers
___
L
On Tue, 2016-23-02 at 11:05:01 UTC, xinhui wrote:
> From: pan xinhui
>
> __xchg_called_with_bad_pointer() can't tell us what codes use {cmp}xchg
> in incorrect way. And no error will be reported until the link stage.
> To fix such a kind of issues easily, we use BUILD_BUG_ON_MSG() here.
>
> Sig
On Thu, 2016-18-02 at 02:48:01 UTC, Balbir Singh wrote:
> Changelog:
> Don't use REGION_ID, breaks on some platforms
> Don't blindly add PAGE_OFFSET to bugaddr
>
> I ran into this issue while debugging an early boot problem.
> The system hit a BUG_ON() but report bug failed to print the
>
Hi Suraj,
On Mon, 2016-29-02 at 06:29:55 UTC, Suraj Jitindar Singh wrote:
> LTO can cause GCC to inline some functions which have attributes set. The
You should define what LTO is the first time you use it.
> act of inlining the functions can lead to GCC forgetting about the
> attributes which l
On Mon, Feb 15, 2016 at 12:55:02PM +1100, Alexey Kardashevskiy wrote:
> These patches enable in-kernel acceleration for H_PUT_TCE_INDIRECT and
> H_STUFF_TCE hypercalls which allow doing multiple (up to 512) TCE entries
> update in a single call saving time on switching context. QEMU already
> suppo
There are certain condition in which H_PROTECT can return error code
other than H_NOT_FOUND and H_SUCCESS. One such being an attempt to
update an hpte owned by adjunct partition. Return 0 in that case so
that user space will retry the access. In adjunct case this mean we
will not make much progress
CHECK_HMI_INTERRUPT is used to check for HMI's in reset vector. Move
the macro to a common location (exception-64s.h)
This patch does not change any functionality.
Signed-off-by: Shreyas B. Prabhu
---
arch/powerpc/include/asm/exception-64s.h | 19 +++
arch/powerpc/kernel/idle_pow
Before entering any idle state which can result in a state loss
we currently save the context in the stack before entering idle.
Encapsulate these steps in a macro IDLE_STATE_PREP. Move this
and other macros to commonly accessible location.
Signed-off-by: Shreyas B. Prabhu
---
arch/powerpc/inclu
In the current code, when the thread wakes up in reset vector, some
of the state restore code and check for whether a thread needs to
branch to kvm is duplicated. Reorder the code such that this
duplication is avoided.
At a higher level this is what the change looks like-
Before this patch -
These patches are purely code movement and cleanup.
There is no functionality change.
Note, there are multiple style error reported for patch 1 and 2.
I think this is because checkpatch script mistakes the patches
as C code because of the presence of semi-colon in each line. I
for now have largely
Le 23/10/2015 05:30, Scott Wood a écrit :
On Tue, 2015-09-22 at 16:34 +0200, Christophe Leroy wrote:
r5 does contain the value to be updated, so lets use r5 all way long
for that. It makes the code more readable.
To avoid confusion, it is better to use adde instead of addc
The first addition
On Mon, Feb 29, 2016 at 11:05 AM, Arnd Bergmann wrote:
> On Friday 26 February 2016 18:41:06 Li Yang wrote:
>> >> >
>> >> > It would be perfect if this it true. But I tried with the following
>> >> > change, it just makes QORIQ_CPUFREQ non-selectable if THERMAL=m.
>> >> >
>> >> > diff --git a/dri
On Monday 29 February 2016 15:33:37 Rafael J. Wysocki wrote:
> >
> > Note the check on !CPU_THERMAL rather than !THERMAL in my patch, that
> > part was correct. I think the line should be
> >
> > depends on !CPU_THERMAL || THERMAL
> >
> > as some other drivers do. I must have copied the lin
On 02/29/2016 03:52 AM, Anshuman Khandual wrote:
> There are certain condition in which H_PROTECT can return error code
> other than H_NOT_FOUND and H_SUCCESS. One such being an attempt to
> update an hpte owned by adjunct partition. Return 0 in that case so
> that user space will retry the access.
Hi all,sorry for this email but i need to ask to Alexander Graf and Michael
Ellerman if will be possible have kvm and kvm-pr for the Freescale/Nix P5020
cpu . We are testing a new desktop machine with this powerpc cpu classesand
right now we see kvm under qemu is working only on emb side, this
On Thu, 2016-02-25 at 11:57 +0100, Alessio Igor Bogani wrote:
> Signed-off-by: Alessio Igor Bogani
> ---
> arch/powerpc/boot/dts/fsl/gef_ppc9a.dts| 284 +++---
> arch/powerpc/boot/dts/fsl/gef_sbc310.dts | 276 +++--
> arch/powerpc/boot/dts/fsl/gef_sbc
On Mon, 2016-29-02 at 11:52:32 UTC, Anshuman Khandual wrote:
> There are certain condition in which H_PROTECT can return error code
> other than H_NOT_FOUND and H_SUCCESS. One such being an attempt to
> update an hpte owned by adjunct partition. Return 0 in that case so
> that user space will retry
On Mon, 29 Feb 2016 17:53:42 +1100
Cyril Bur wrote:
Apologies this should have had a Version 6 prefix!
> Cover-letter for V1 of the series is at
> https://lists.ozlabs.org/pipermail/linuxppc-dev/2015-November/136350.html
>
> Cover-letter for V2 of the series is at
> https://lists.ozlabs.org/p
On Mon, 29 Feb 2016 22:10:13 +1100 (AEDT)
Michael Ellerman wrote:
> Hi Suraj,
>
> On Mon, 2016-29-02 at 06:29:55 UTC, Suraj Jitindar Singh wrote:
> > LTO can cause GCC to inline some functions which have attributes set. The
>
> You should define what LTO is the first time you use it.
>
> > a
On Tue, 2016-03-01 at 10:08 +1100, Cyril Bur wrote:
> On Mon, 29 Feb 2016 22:10:13 +1100 (AEDT)
> Michael Ellerman wrote:
> > On Mon, 2016-29-02 at 06:29:55 UTC, Suraj Jitindar Singh wrote:
> > > Both these cases are hard to detect and require manual inspection of
> > > binaries which is unlikely
Hi Michael,
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.5-rc6 next-20160229]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Michael-Ellerman/powerpc-Create-a-helper
On Tue, 2016-09-02 at 03:32:42 UTC, David Gibson wrote:
> This makes a number of cleanups to handling of mapping failures during
> memory hotplug on Power:
>
> For errors creating the linear mapping for the hot-added region:
> * This is now reported with EFAULT which is more appropriate than the
On Tue, Mar 01, 2016 at 12:59:07PM +1100, Michael Ellerman wrote:
> On Tue, 2016-09-02 at 03:32:42 UTC, David Gibson wrote:
> > This makes a number of cleanups to handling of mapping failures during
> > memory hotplug on Power:
> >
> > For errors creating the linear mapping for the hot-added region
On Mon, 29 Feb 2016 22:10:13 +1100 (AEDT)
Michael Ellerman wrote:
> Hi Suraj,
>
> On Mon, 2016-29-02 at 06:29:55 UTC, Suraj Jitindar Singh wrote:
> > LTO can cause GCC to inline some functions which have attributes set. The
>
> You should define what LTO is the first time you use it.
>
> > a
This series move book3s config with 64k linux page size to a 4 level
linux page table setup. This makes it similar to PowerISA 3.0 radix
setup which inturn will enable us to support both hash and radix
MMU model using single kernel.
Aneesh Kumar K.V (3):
powerpc/mm: Split pgtable types to separ
We move the page table accessors into a separate header. We will
later add a big endian variant of the table which is needed for radix.
No functionality change only code movement.
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/page.h | 104 +---
We remove real_pte_t out of STRICT_MM_TYPESCHECK.
Reviewed-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgtable.h | 5 -
arch/powerpc/include/asm/pgtable-types.h | 26 +-
2 files changed, 9 insertions(+), 22 deletions
This is needed so that we can support both hash and radix page table
using single kernel. Radix kernel uses a 4 level table.
We now use physical address in upper page table tree levels. Even though
they are aligned to their size, for the masked bits we use the
bit positions as per PowerISA 3.0.
S
From: "Kirill A. Shutemov"
With next generation power processor, we are having a new mmu model
[1] that require us to maintain a different linux page table format.
Inorder to support both current and future ppc64 systems with a single
kernel we need to make sure kernel can select between differe
Excerpt from man 2 perf_event_open:
/proc/sys/kernel/perf_event_paranoid
The perf_event_paranoid file can be set to restrict access to the
performance counters.
2 allow only user-space measurements.
1 allow both kernel and user measurements (default).
0 allow access to CPU-specific
On 02/29/2016 10:20 PM, Tyrel Datwyler wrote:
> On 02/29/2016 03:52 AM, Anshuman Khandual wrote:
>> There are certain condition in which H_PROTECT can return error code
>> other than H_NOT_FOUND and H_SUCCESS. One such being an attempt to
>> update an hpte owned by adjunct partition. Return 0 in th
On 01/03/16 14:11, Cyril Bur wrote:
> On Mon, 29 Feb 2016 22:10:13 +1100 (AEDT)
> Michael Ellerman wrote:
>
>> Hi Suraj,
>>
>> On Mon, 2016-29-02 at 06:29:55 UTC, Suraj Jitindar Singh wrote:
>>> LTO can cause GCC to inline some functions which have attributes set. The
>> You should define what L
Tyrel Datwyler writes:
> On 02/29/2016 03:52 AM, Anshuman Khandual wrote:
>> There are certain condition in which H_PROTECT can return error code
>> other than H_NOT_FOUND and H_SUCCESS. One such being an attempt to
>> update an hpte owned by adjunct partition. Return 0 in that case so
>> that us
On 03/01/2016 04:31 AM, Michael Ellerman wrote:
> On Mon, 2016-29-02 at 11:52:32 UTC, Anshuman Khandual wrote:
>> There are certain condition in which H_PROTECT can return error code
>> other than H_NOT_FOUND and H_SUCCESS. One such being an attempt to
>> update an hpte owned by adjunct partition.
Balbir Singh writes:
> On 26/02/16 14:53, Aneesh Kumar K.V wrote:
>> This enables us to share the same page table code for
>> both radix and hash. Radix use a hardware defined big endian
> ^uses
>> page table
>>
>> Asm -> C conversion makes it simpler to build code fo
On 03/01/2016 10:57 AM, Aneesh Kumar K.V wrote:
> Tyrel Datwyler writes:
>
>> > On 02/29/2016 03:52 AM, Anshuman Khandual wrote:
>>> >> There are certain condition in which H_PROTECT can return error code
>>> >> other than H_NOT_FOUND and H_SUCCESS. One such being an attempt to
>>> >> update an h
From: Mahesh Salgaonkar
Move IDLE_STATE_ENTER_SEQ macro to cpuidle.h so that MCE handler changes
in subsequent patch can use it.
No functionality change.
Signed-off-by: Mahesh Salgaonkar
---
arch/powerpc/include/asm/cpuidle.h | 14 ++
arch/powerpc/kernel/idle_power7.S | 12 --
From: Mahesh Salgaonkar
The routine machine_check_pSeries_early() is only used on powernv, not
pseries. Hence rename machine_check_pSeries_early to
machine_check_powernv_early.
Reported-by: Paul Mackerras
Signed-off-by: Mahesh Salgaonkar
---
arch/powerpc/kernel/exceptions-64s.S |4 ++--
1
From: Mahesh Salgaonkar
The current implementation of MCE early handling modifies CR0/1 registers
without saving its old values. Fix this by moving early check for
powersaving mode to machine_check_handle_early().
The power architecture 2.06 or later allows the possibility of getting
machine che
Currently the assembly to save and restore VSX registers boils down to a
load immediate of the offset of the specific VSX register in memory
followed by the load/store which repeats in sequence for each VSX register.
This patch attempts to do better by loading up four registers with
immediates so
Currently the assembly to save and restore Altivec registers boils down to
a load immediate of the offset of the specific Altivec register in memory
followed by the load/store which repeats in sequence for each Altivec
register.
This patch attempts to do better by loading up four registers with
im
This adds a capability number for 64-bit TCE tables support.
Signed-off-by: Alexey Kardashevskiy
---
include/uapi/linux/kvm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 9da9051..8ce5f64 100644
--- a/include/uapi/linux/kvm.h
+++ b
This extends the existing H_PUT_TCE/etc in-kernel acceleration to 64bit
DMA windows mapped at addresses other than zero. This accelerates huge
DMA windows which pseries guests create using Dynamic DMA window (DDW) API.
This does not affect VFIO yet.
This is made against
git://git.kernel.org/pub/
This enables userspace view of TCE tables to start from non-zero offset
on a bus. This will be used for huge DMA windows.
This only changes the internal structure, the user interface needs to
change in order to use an offset.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
---
ar
At the moment the kvmppc_spapr_tce_table struct can only describe
4GB windows and handle fixed size (4K) pages. Dynamic DMA windows
support more so these limits need to be extended.
This replaces window_size (in bytes, 4GB max) with page_shift (32bit)
and size (64bit, in pages).
This should cause
The existing KVM_CREATE_SPAPR_TCE only supports 32bit windows which is not
enough for directly mapped windows as the guest can get more than 4GB.
This adds KVM_CREATE_SPAPR_TCE_64 ioctl and advertises it
via KVM_CAP_SPAPR_TCE_64 capability. The table size is checked against
the locked memory limit
Add IC, SI and SIRAM document of QE to
Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
Signed-off-by: Zhao Qiang
---
Changes for v2
- Add interrupt-controller in Required properties
- delete address-cells and size-cells for qe-si and qe-siram
Changes for v3
- A
Add ucc hdlc document to
Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt
Signed-off-by: Zhao Qiang
---
Changes for v2
- use ucc-hdlc instead of ucc_hdlc
- add more information to properties.
Changes for v3
- use fsl,tx-timeslot-mask instead of fsl,tx-times
Add uqe_serial document to
Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
Signed-off-by: Zhao Qiang
---
Changes for v2
- modify tx/rx-clock-name specification
Changes for v2
- NA
.../bindings/powerpc/fsl/cpm_qe/uqe_serial.txt| 19 +++
We are updating pte in those functions.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash64_4k.c | 2 +-
arch/powerpc/mm/hash64_64k.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/mm/hash64_4k.c b/arch/powerpc/mm/hash64_4k.c
index e7c04542ba62..e3e
We don't need to update linux page table entry with _PAGE_HASHPTE early
in hash pte fault. A parallel pte update will loop via _PAGE_BUSY
and look at _PAGE_HASHPTE for a required hpte flush only if
_PAGE_BUSY is cleared. That ensures a pte update will wait for a
parallel hpte insert to finish befor
This should not have any impact for hash linux implementation. But radix
would require us to flush tlb after clearing accessed bit. Also move
code that is not dependent on pte bits to generic header.
We use the generic version of ptep_clear_flush_young here.
Signed-off-by: Aneesh Kumar K.V
---
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/{mmu-hash32.h => book3s/32/mmu-hash.h} | 0
arch/powerpc/include/asm/{mmu-hash64.h => book3s/64/mmu-hash.h} | 0
arch/powerpc/include/asm/mmu.h | 4 ++--
arch/powerpc/kernel/cpu_setup_power.S
This moves kernel page mapping, page table cache init and vmemmap
routines to hash64 file. For hash we don't create linux page table
entries for linear mapping and having then in a separate file like
pgtable-hash64.c helps. This also help in adding radix routines later.
Signed-off-by: Aneesh Kumar
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/pgtable-hash64.c | 373 +++
arch/powerpc/mm/pgtable_64.c | 373 ---
2 files changed, 373 insertions(+), 373 deletions(-)
diff --git a/arch/powerpc/mm/pgtable-hash64.c b
This series include changes that should help in implementing
radix MMU model. Besides that, we also try to consolidate
hash64 code into separate files wherever it simplifies
the existing code by removing #ifdef around C code. IMHO
code movement also helps in indicating supported features
on differe
The radix variant is going to require a flush_tlb_range. We can't then
have this as static inline because of the usage of HPAGE_PMD_SIZE. So
we are forced to make it a function in which case we can use the generic
version.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/p
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/tlbflush-hash.h | 94 ++
arch/powerpc/include/asm/tlbflush.h| 92 +
2 files changed, 95 insertions(+), 91 deletions(-)
create mode 100644 arch/powerpc/include/asm/book3s
add qe node to t104xrdb.dtsi
Signed-off-by: Zhao Qiang
---
Changes for v2
- rebase
Changes for v3
- rebase
arch/powerpc/boot/dts/fsl/t104xrdb.dtsi | 39 +
1 file changed, 39 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/t104xrdb.dtsi
b/ar
add qe node to t104xd4rdb.dtsi and t1040si-post.dtsi.
Signed-off-by: Zhao Qiang
---
Changes for v2
- rebase
Changes for v3
- rebase
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 45 +
arch/powerpc/boot/dts/fsl/t104xd4rdb.dtsi | 39 ++
add qe node to t104xqds.dtsi
Signed-off-by: Zhao Qiang
---
Changes for v2
- rebase
Changes for v3
- rebase
arch/powerpc/boot/dts/fsl/t104xqds.dtsi | 39 +
1 file changed, 39 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/t104xqds.dtsi
b/ar
cpm_qe is supported on both powerpc and arm.
and the QE code has been moved from arch/powerpc into
drivers/soc/fsl, so move cpm_qe binding from powerpc/fsl
to soc/fsl
Signed-off-by: Zhao Qiang
---
Changes for v3
- NA
Documentation/devicetree/bindings/{powerpc => soc}/fsl/cpm_qe/cpm.txt
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