Hi Wen,
2012/07/06 18:20, Wen Congyang wrote:
> At 07/06/2012 04:27 PM, Yasuaki Ishimatsu Wrote:
>> Hi Wen,
>>
>> 2012/07/04 19:01, Wen Congyang wrote:
>>> At 07/04/2012 01:52 PM, Yasuaki Ishimatsu Wrote:
Hi Wen,
2012/07/04 14:08, Wen Congyang wrote:
> At 07/04/2012 12:45 PM, Ya
This patchset adds/fixes the following functionality specific to the
FSL MPIC:
1. Fix support for timer group B interrupts. Previously these were
not getting initialized.
2. Use the MPIC_LARGE_VECTORS flag while intializing FSL MPIC.
This prevents us from eating in to hardware vector number
space
Previously, these interrupts would be mapped, but the offset
calculation was broken, and only the first group was initialized.
Signed-off-by: Scott Wood
---
arch/powerpc/include/asm/mpic.h |5 +++
arch/powerpc/sysdev/mpic.c | 58 ---
2 files changed
We should use the MPIC_LARG_VECTORS flag while intializing the MPIC.
This prevents us from eating in to hardware vector number space (MSIs)
while setting up internal sources.
Signed-off-by: Varun Sethi
---
arch/powerpc/sysdev/mpic.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
d
All SOC device error interrupts are muxed and delivered to the core as a single
MPIC error interrupt. Currently all the device drivers requiring access to
device
errors have to register for the MPIC error interrupt as a shared interrupt.
With this patch we add interrupt demuxing capability in the
This patch series aims to support physical memory hot-remove.
[RFC PATCH v3 1/13] memory-hotplug : rename remove_memory to offline_memory
[RFC PATCH v3 2/13] memory-hotplug : add physical memory hotplug code to
acpi_memory_device_remove
[RFC PATCH v3 3/13] memory-hotplug : unify argument of
remove_memory() does not remove memory but just offlines memory. The patch
changes name of it to offline_memory().
CC: David Rientjes
CC: Jiang Liu
CC: Len Brown
CC: Benjamin Herrenschmidt
CC: Paul Mackerras
CC: Christoph Lameter
Cc: Minchan Kim
CC: Andrew Morton
CC: KOSAKI Motohiro
CC: W
acpi_memory_device_remove() has been prepared to remove physical memory.
But, the function only frees acpi_memory_device currentlry.
The patch adds following functions into acpi_memory_device_remove():
- offline memory
- remove physical memory (only return -EBUSY)
- free acpi_memory_device
There are two ways to create /sys/firmware/memmap/X sysfs:
- firmware_map_add_early
When the system starts, it is calledd from e820_reserve_resources()
- firmware_map_add_hotplug
When the memory is hot plugged, it is called from add_memory()
But these functions are called without unif
When (hot)adding memory into system, /sys/firmware/memmap/X/{end, start, type}
sysfs files are created. But there is no code to remove these files. The patch
implements the function to remove them.
Note : The code does not free firmware_map_entry since there is no way to free
memory which i
Since applying a patch(de7f0cba96786c), release_mem_region() has been changed
as called in PAGES_PER_SECTION chunks because register_memory_resource() is
called in PAGES_PER_SECTION chunks by add_memory(). But it seems firmware
dependency. If CRS are written in the PAGES_PER_SECTION chunks in ACPI
When calling remove_memory_block(), the function shows following message at
device_release().
Device 'memory528' does not have a release() function, it is broken and must
be fixed.
remove_memory_block() calls kfree(mem). I think it shouled be called from
device_release(). So the patch implements
The patch adds __remove_pages() to remove_memory(). Then the range of
phys_start_pfn argument and nr_pages argument in __remove_pagse() may
have different zone. So zone argument is removed from __remove_pages()
and __remove_pages() caluculates zone in each section.
When CONFIG_SPARSEMEM_VMEMMAP is
There is a possibility that get_page_bootmem() is called to the same page many
times. So when get_page_bootmem is called to the same page, the function only
increments page->_count.
CC: David Rientjes
CC: Jiang Liu
CC: Len Brown
CC: Benjamin Herrenschmidt
CC: Paul Mackerras
CC: Christoph Lame
For implementing register_page_bootmem_info_node of sparse-vmemmap,
register_page_bootmem_info_node and put_page_bootmem are moved to
memory_hotplug.c
CC: David Rientjes
CC: Jiang Liu
CC: Len Brown
CC: Benjamin Herrenschmidt
CC: Paul Mackerras
CC: Christoph Lameter
Cc: Minchan Kim
CC: Andre
For removing memmap region of sparse-vmemmap which is allocated bootmem,
memmap region of sparse-vmemmap needs to be registered by get_page_bootmem().
So the patch searches pages of virtual mapping and registers the pages by
get_page_bootmem().
CC: David Rientjes
CC: Jiang Liu
CC: Len Brown
CC:
I don't think that all pages of virtual mapping in removed memory can be
freed, since page which type is MIX_SECTION_INFO is difficult to free.
So, the patch only frees page which type is SECTION_INFO at first.
CC: David Rientjes
CC: Jiang Liu
CC: Len Brown
CC: Benjamin Herrenschmidt
CC: Paul
When calling unregister_node(), the function shows following message at
device_release().
Device 'node2' does not have a release() function, it is broken and must be
fixed.
So the patch implements node_device_release()
CC: David Rientjes
CC: Jiang Liu
CC: Len Brown
CC: Benjamin Herrenschmidt
The patch adds node_set_offline() and unregister_one_node() to remove_memory()
for removing sysfs file of node.
CC: David Rientjes
CC: Jiang Liu
CC: Len Brown
CC: Benjamin Herrenschmidt
CC: Paul Mackerras
CC: Christoph Lameter
Cc: Minchan Kim
CC: Andrew Morton
CC: KOSAKI Motohiro
CC: Wen
On some platforms, in RC mode, root port has neither MSI/MSI-X nor INTx
interrupt generated, which are available only in EP mode on those platform.
In this case, we try to use other interrupt if supported (i.e. there is the
shared error interrupt on platform P1010, P3041, P4080, etc) to have AER,
H
Modifications are aimed specifically at the e500mc/e5500 cpu setup code.
Following modifications are introduced by this patchset:
1. Move the E.HV check to the cpu setup code. Based on this check we manipulte
the
CPU_FTR_EMB_HV flag (added as a part of e500mc KVM support) in the cpu_spec
st
Move the E.HV check and CPU_FTR_EMB_HV flag manipulation to the cpu setup code.
Create a separate routine for E.HV ivors setup.
Signed-off-by: Varun Sethi
---
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 29 ++---
arch/powerpc/kernel/head_fsl_booke.S | 18
Merge the 32 bit cpu setup code for e500mc/e5500 and define the "cpu_restore"
routine (for e5500/e6500) only for the 64 bit case. The cpu_restore routine
is used in the 64 bit case for setting up the secondary cores.
Signed-off-by: Varun Sethi
---
arch/powerpc/kernel/cpu_setup_fsl_booke.S |1
For the 64 bit case separate out e5500 cpu_setup and cpu_restore functions.
The cpu_setup function (for the primary core) is passed the cpu_spec pointer,
which is not there in case of the cpu_restore function. Also, in our case
we will have to manipulate the CPU_FTR_EMB_HV flag on the the primary c
Added CPU_FTR_EMB_HV feature check for e550.
Signed-off-by: Varun Sethi
Signed-off-by: Mihai Caraman
---
arch/powerpc/kernel/cpu_setup_fsl_booke.S |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
b/arch/powerpc/kernel/cpu_s
Hi,
This patchset include patches for supporting 64TB with ppc64. I haven't booted
this on hardware with 64TB memory yet. But they boot fine on real hardware with
less memory. Changes extend VSID bits to 38 bits for a 256MB segment
and 26 bits for 1TB segments.
Changes from V2:
* Fix few FIXMEs
From: "Aneesh Kumar K.V"
This patch convert different functions to take virtual page number
instead of virtual address. Virtual page number is virtual address
shifted right by VPN_SHIFT (12) bits. This enable us to have an
address range of upto 76 bits.
Signed-off-by: Aneesh Kumar K.V
---
arch
From: "Aneesh Kumar K.V"
ISA doc doesn't talk about this. As per ISA doc for a 4K page
tlbie RB RS
" The Abbreviated Virtual Address (AVA) field in register RB must
contain bits 14:65 of the virtual address translated by the TLB
entry to be invalidated."
That indicate we should not ma
From: "Aneesh Kumar K.V"
Rename the variable to better reflect the values. No functional change
in this patch.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s.h |2 +-
arch/powerpc/include/asm/machdep.h |6 +--
arch/powerpc/include/asm/mmu-hash64.h |
From: "Aneesh Kumar K.V"
This patch simplify hpte_decode for easy switching of virtual address to
virtual page number in the later patch
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_native_64.c | 49 ++
1 file changed, 28 insertions(+), 21 dele
From: "Aneesh Kumar K.V"
As we keep increasing PGTABLE_RANGE we need not increase the virual
map area for kernel.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable-ppc64.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/pgtable
From: "Aneesh Kumar K.V"
Don't open code the same
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/cell/beat_htab.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/cell/beat_htab.c
b/arch/powerpc/platforms/cell/beat_htab.c
index 943c9d3.
From: "Aneesh Kumar K.V"
This patch makes the high psizes mask as an unsigned char array
so that we can have more than 16TB. Currently we support upto
64TB
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h |6 ++-
arch/powerpc/include/asm/page_64.h|6 ++-
ar
From: "Aneesh Kumar K.V"
With larger vsid we need to track more bits of ESID in slb cache
for slb invalidate.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/paca.h |2 +-
arch/powerpc/mm/slb_low.S |8
2 files changed, 5 insertions(+), 5 deletions(-)
diff -
From: "Aneesh Kumar K.V"
Increase max addressable range to 64TB. This is not tested on
real hardware yet.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h|8
arch/powerpc/include/asm/pgtable-ppc64-4k.h |2 +-
arch/powerpc/include/asm/pgtable-p
From: "Aneesh Kumar K.V"
Increase the number of valid VSID bits in slbmte instruction.
We will use the new bits when we increase valid VSID bits.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/slb_low.S |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerp
From: "Aneesh Kumar K.V"
slice array size and slice mask size depend on PGTABLE_RANGE. We
can't directly include pgtable.h in these header because there is
a circular dependency. So add compile time check for these values.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64
> I was pointed by Glauber to the slab common code patches. I need some
> more time to read the patches. Now I think the slab/slot changes in this
> v3 are not needed, and can be ignored.
That may take some kernel cycles. You have a current issue here that needs
to be fixed.
> > down_write(&
On Jul 9, 2012, at 3:45 AM, Varun Sethi wrote:
> Previously, these interrupts would be mapped, but the offset
> calculation was broken, and only the first group was initialized.
>
> Signed-off-by: Scott Wood
> ---
> arch/powerpc/include/asm/mpic.h |5 +++
> arch/powerpc/sysdev/mpic.c |
On Jul 9, 2012, at 3:46 AM, Varun Sethi wrote:
> We should use the MPIC_LARG_VECTORS flag while intializing the MPIC.
> This prevents us from eating in to hardware vector number space (MSIs)
> while setting up internal sources.
>
> Signed-off-by: Varun Sethi
> ---
> arch/powerpc/sysdev/mpic.c
> -Original Message-
> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
> Sent: Monday, July 09, 2012 7:58 PM
> To: Sethi Varun-B16395
> Cc: linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH 2/3 v2] powerpc/mpic: Use the MPIC_LARGE_VECTORS flag
> for FSL MPIC.
>
>
> On Jul 9, 2012,
On Mon, 9 Jul 2012, Yasuaki Ishimatsu wrote:
> Even if you apply these patches, you cannot remove the physical memory
> completely since these patches are still under development. I want you to
> cooperate to improve the physical memory hot-remove. So please review these
> patches and give your c
On 07/09/2012 05:49 AM, Shengzhou Liu wrote:
> On some platforms, in RC mode, root port has neither MSI/MSI-X nor INTx
> interrupt generated, which are available only in EP mode on those platform.
> In this case, we try to use other interrupt if supported (i.e. there is the
> shared error interrupt
On 07/09/2012 09:12 AM, Kumar Gala wrote:
>
> On Jul 9, 2012, at 3:45 AM, Varun Sethi wrote:
>
>> Previously, these interrupts would be mapped, but the offset
>> calculation was broken, and only the first group was initialized.
>>
>> Signed-off-by: Scott Wood
>> ---
>> arch/powerpc/include/asm/m
On Sun, Jul 08, 2012 at 07:55:55PM +0200, Kay Sievers wrote:
> On Sat, 2012-07-07 at 07:04 +1000, Michael Neuling wrote:
> > Whole kmsg below.
>
> I guess I have an idea now what's going on.
>
> > 4,47,0;WARNING: at
> > /scratch/mikey/src/linux-ozlabs/arch/powerpc/sysdev/xics/xics-common.c:105
>
On Mon, 2012-07-09 at 10:09 -0700, Greg Kroah-Hartman wrote:
> is it ok if we
> just merge this in 3.6-rc1 and backport it to 3.5.1 if it looks ok
> there?
I'd prefer it get accepted now so that refactoring the
printk subsystem could occur for 3.6.
Another option would be to revert all Kay's chan
On Jul 9, 2012, at 11:43 AM, Scott Wood wrote:
> On 07/09/2012 09:12 AM, Kumar Gala wrote:
>>
>> On Jul 9, 2012, at 3:45 AM, Varun Sethi wrote:
>>
>>> Previously, these interrupts would be mapped, but the offset
>>> calculation was broken, and only the first group was initialized.
>>>
>>> Sign
On 07/09/2012 12:36 PM, Kumar Gala wrote:
>
> On Jul 9, 2012, at 11:43 AM, Scott Wood wrote:
>
>> On 07/09/2012 09:12 AM, Kumar Gala wrote:
>>>
>>> On Jul 9, 2012, at 3:45 AM, Varun Sethi wrote:
>>>
Previously, these interrupts would be mapped, but the offset
calculation was broken, and
On Jul 9, 2012, at 3:47 AM, Varun Sethi wrote:
> All SOC device error interrupts are muxed and delivered to the core as a
> single
> MPIC error interrupt. Currently all the device drivers requiring access to
> device
> errors have to register for the MPIC error interrupt as a shared interrupt.
Trying to get the pciehp module to work on the above system.
I can see it register but then nothing happens. I suspect there is
something missing that I don't see ATM. Any clues what to look for?
Jocke
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Linuxppc-dev@lists.
On 07/09/2012 02:03 PM, Kumar Gala wrote:
>
> On Jul 9, 2012, at 3:47 AM, Varun Sethi wrote:
>
>> +int mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum)
>> +{
>
> Why can't we do this during mpic_init() time?
Are you willing to hardcode that IRQ 16 is the error interrupt, without
wai
On Sun, 2012-07-08 at 19:55 +0200, Kay Sievers wrote:
> At the same time the CPU#2 prints the same warning with a continuation
> line, but the buffer from CPU#1 can not be flushed to the console, nor
> can the continuation line printk()s from CPU#2 be merged at this point.
> The consoles are still
On Mon, Jul 9, 2012 at 11:42 PM, Joe Perches wrote:
> On Sun, 2012-07-08 at 19:55 +0200, Kay Sievers wrote:
>
>> At the same time the CPU#2 prints the same warning with a continuation
>> line, but the buffer from CPU#1 can not be flushed to the console, nor
>> can the continuation line printk()s f
On Tue, 2012-07-10 at 00:10 +0200, Kay Sievers wrote:
> On Mon, Jul 9, 2012 at 11:42 PM, Joe Perches wrote:
> > On Sun, 2012-07-08 at 19:55 +0200, Kay Sievers wrote:
> >
> >> At the same time the CPU#2 prints the same warning with a continuation
> >> line, but the buffer from CPU#1 can not be flus
Greg Kroah-Hartman wrote:
> On Sun, Jul 08, 2012 at 07:55:55PM +0200, Kay Sievers wrote:
> > On Sat, 2012-07-07 at 07:04 +1000, Michael Neuling wrote:
> > > Whole kmsg below.
> >
> > I guess I have an idea now what's going on.
> >
> > > 4,47,0;WARNING: at
> > > /scratch/mikey/src/linux-ozlabs/
On Tue, Jul 10, 2012 at 12:29 AM, Joe Perches wrote:
> On Tue, 2012-07-10 at 00:10 +0200, Kay Sievers wrote:
>> On Mon, Jul 9, 2012 at 11:42 PM, Joe Perches wrote:
>> > On Sun, 2012-07-08 at 19:55 +0200, Kay Sievers wrote:
>> >
>> >> At the same time the CPU#2 prints the same warning with a conti
Hi Aneesh,
On Mon, 9 Jul 2012 18:43:33 +0530 "Aneesh Kumar K.V"
wrote:
>
> diff --git a/arch/powerpc/include/asm/mmu-hash64.h
> b/arch/powerpc/include/asm/mmu-hash64.h
> index 1c65a59..1c984a6 100644
> --- a/arch/powerpc/include/asm/mmu-hash64.h
> +++ b/arch/powerpc/include/asm/mmu-hash64.h
>
Hi Aneesh,
On Mon, 9 Jul 2012 18:43:33 +0530 "Aneesh Kumar K.V"
wrote:
>
> diff --git a/arch/powerpc/mm/hash_native_64.c
> b/arch/powerpc/mm/hash_native_64.c
> index 660b8bb..308e29d 100644
> --- a/arch/powerpc/mm/hash_native_64.c
> +++ b/arch/powerpc/mm/hash_native_64.c
> @@ -39,22 +39,33 @@
On Tue, 2012-07-10 at 00:40 +0200, Kay Sievers wrote:
> On Tue, Jul 10, 2012 at 12:29 AM, Joe Perches wrote:
> > On Tue, 2012-07-10 at 00:10 +0200, Kay Sievers wrote:
> >> On Mon, Jul 9, 2012 at 11:42 PM, Joe Perches wrote:
> >> > On Sun, 2012-07-08 at 19:55 +0200, Kay Sievers wrote:
> >> >
> >>
On Mon, 2012-07-09 at 16:32 -0700, Joe Perches wrote:
> Then you've changed semantics and I think you need to
> fix it.
>
> A dev_ call is not guaranteed to be a complete
> message.
>
> There are dev_ and netdev_ calls
> followed by pr_cont.
>
> Maybe these could be fixed up and then they could
On Mon, 2012-07-09 at 09:01 -0500, Christoph Lameter wrote:
> > I was pointed by Glauber to the slab common code patches. I need some
> > more time to read the patches. Now I think the slab/slot changes in this
> > v3 are not needed, and can be ignored.
>
> That may take some kernel cycles. You ha
On Jul 9, 2012, at 3:22 PM, Scott Wood wrote:
> On 07/09/2012 02:03 PM, Kumar Gala wrote:
>>
>> On Jul 9, 2012, at 3:47 AM, Varun Sethi wrote:
>>
>>> +int mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum)
>>> +{
>>
>> Why can't we do this during mpic_init() time?
>
> Are you willin
Hi Geoff !
Do you have access to any kind of documentation regarding the precise
semantics of lv1_pause() ?
I'm fixing various issues with our idle loops, among other things,
because we are soft-disabled when we hit ppc_md.powersave() but not
hard-disabled, there could be an interrupt marked as p
Looks like we still have issues with pSeries and Cell idle code
vs. the lazy irq state. In fact, the reset fixes that went upstream
are exposing the problem more by causing BUG_ON() to trigger (which
this patch turns into a WARN_ON instead).
We need to be careful when using a variant of low power
Benjamin Herrenschmidt wrote:
> Looks like we still have issues with pSeries and Cell idle code
> vs. the lazy irq state. In fact, the reset fixes that went upstream
> are exposing the problem more by causing BUG_ON() to trigger (which
> this patch turns into a WARN_ON instead).
Do we need to cc
Stephen Rothwell writes:
> Hi Aneesh,
>
> On Mon, 9 Jul 2012 18:43:33 +0530 "Aneesh Kumar K.V"
> wrote:
>>
>> diff --git a/arch/powerpc/include/asm/mmu-hash64.h
>> b/arch/powerpc/include/asm/mmu-hash64.h
>> index 1c65a59..1c984a6 100644
>> --- a/arch/powerpc/include/asm/mmu-hash64.h
>> +++ b/
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, July 10, 2012 12:39 AM
> To: Liu Shengzhou-B36685
> Cc: bhelg...@google.com; linux-...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org
> Subject: Re: [PATCH] PCI: Add pcie_irq=other to enable non MSI/INTx interrupt
> for p
Stephen Rothwell writes:
> Hi Aneesh,
>
> On Mon, 9 Jul 2012 18:43:33 +0530 "Aneesh Kumar K.V"
> wrote:
>>
>> diff --git a/arch/powerpc/mm/hash_native_64.c
>> b/arch/powerpc/mm/hash_native_64.c
>> index 660b8bb..308e29d 100644
>> --- a/arch/powerpc/mm/hash_native_64.c
>> +++ b/arch/powerpc/mm
The following 4 patches enabling fsl-dma and talitos offload raid
operations for improving raid performance and balancing CPU load.
Write performance will be improved by 40% tested by iozone. CPU load
will be reduced by 8%.
Qiang Liu (4):
Talitos: move the data structure into header file
The following 4 patches enabling fsl-dma and talitos offload raid
operations for improving raid performance and balancing CPU load.
Write performance will be improved by 40% tested by iozone. CPU load
will be reduced by 8%.
Qiang Liu (4):
Talitos: move the data structure into header file
Move the declaration of talitos data structure into talitos.h.
Cc: Herbert Xu
Cc: David S. Miller
Signed-off-by: Qiang Liu
---
drivers/crypto/talitos.c | 108 --
drivers/crypto/talitos.h | 108 ++
2 files
Expose Talitos's XOR functionality to be used for RAID parity
calculation via the Async_tx layer.
Cc: Herbert Xu
Cc: David S. Miller
Signed-off-by: Dipen Dudhat
Signed-off-by: Maneesh Gupta
Signed-off-by: Kim Phillips
Signed-off-by: Vishnu Suresh
Signed-off-by: Qiang Liu
---
drivers/crypto
- delete attribute of DMA_INTERRUPT because fsl-dma doesn't support
this function, exception will be thrown if talitos is used to compute xor
at the same time;
- change the release process of dma descriptor for avoiding exception when
enable config NET_DMA, release dma descriptor from 1st to last s
An error will be happened when test with mass data:
"DMA-API: device driver tries to sync DMA memory it has not allocated";
"DMA-API: debugging out of memory - disabling"
dma mapping memory of request->desc is not released by right device,
it should be private->dev but not dev;
Cc: Herbert Xu
Cc:
The following 4 patches enabling fsl-dma and talitos offload raid
operations for improving raid performance and balancing CPU load.
Write performance will be improved by 40% tested by iozone. CPU load
will be reduced by 8%.
Qiang Liu (4):
Talitos: move the data structure into header file
The issue log on core1 is:
root@mpc8572ds:~# ifconfig eth0 10.192.208.244
net eth0: could not attach to PHY
SIOCSIFFLAGS: No such device
To attach PHY node mdio@24520 should not be disabled in dts of core1.
Because all PHYs are controlled through this node as follows:
mdio@24520 {
phy0: e
With 2-cell format interrupts of MSI PCIe ethernet card can not work.
Signed-off-by: Li Yang
Signed-off-by: Jia Hongtao
---
arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts |8
arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts |8
2 files changed, 8 insertions(+), 8 deletio
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