Hi,
I noticed a few crashes on this PowerBook G4 lately, starting somewhere in
3.2.0-rc1. The crashes are really rare and as I'm not on the system all
the time I did not notice most of them. By the time I did, the screen was
blank already and I had to hard-reset the box. But not this time:
h
From: Liu Shuo
Freescale FCM controller has a 2K size limitation of buffer RAM. In order
to support the Nand flash chip whose page size is larger than 2K bytes,
we read/write 2k data repeatedly by issuing FIR_OP_RB/FIR_OP_WB and save
them to a large buffer.
Signed-off-by: Liu Shuo
Signed-off-by
From: Liu Shuo
If we use the Nand flash chip whose number of pages in a block is greater
than 64(for large page), we must treat the low bit of FBAR as being the
high bit of the page address due to the limitation of FCM, it simply uses
the low 6-bits (for large page) of the combined block/page add
From: Liu Shuo
fix whitespaces,tabs coding style issue and use #include instead
of
in drivers/mtd/nand/fsl_elbc.c.
Signed-off-by: Liu Shuo
Signed-off-by: Li Yang
---
drivers/mtd/nand/fsl_elbc_nand.c | 194 +++---
1 files changed, 97 insertions(+), 97 deleti
> fix whitespaces,tabs coding style issue and ...
In my opinion this code was already correct, and would display correctly
at any TAB setting. This patch changes it so that it displays
incorrectly
at all TAB settings other than 8.
Example:
Correct:
function(arg1,
<9spaces>arg2
Incorrect:
functi
On Tue, 2011-11-15 at 11:26 +, Jenkins, Clive wrote:
> > fix whitespaces,tabs coding style issue and ...
>
> In my opinion this code was already correct, and would display correctly
> at any TAB setting. This patch changes it so that it displays
> incorrectly at all TAB settings other than 8.
> > > fix whitespaces,tabs coding style issue and ...
> >
> > In my opinion this code was already correct, and would display correctly
> > at any TAB setting. This patch changes it so that it displays
> > incorrectly at all TAB settings other than 8.
>
> Any tab setting other than 8 is incorrect a
> On Tue, 2011-11-15 at 11:26 +, Jenkins, Clive wrote:
> > > fix whitespaces,tabs coding style issue and ...
> >
> > In my opinion this code was already correct, and would display
correctly
> > at any TAB setting. This patch changes it so that it displays
> > incorrectly at all TAB settings
On Tue, 2011-11-15 at 14:42 +, Jenkins, Clive wrote:
> This may be your (not so humble :-) opinion, and I happen to agree that
> a tab setting of 8 is best, usually. However, as Linus says in his
> coding style document "Coding style is very personal, and I won't _force_
> my views on anybody".
On Nov 14, 2011, at 11:17 PM, Baruch Siach wrote:
> Hi Andy,
>
> On Mon, Nov 14, 2011 at 09:04:47PM +, Fleming Andy-AFLEMING wrote:
>> Well, this got applied quickly, so I guess I can't NAK, but this requires
>> discussion.
>>
>> On Nov 14, 2011, at 0:22, "Baruch Siach" wrote:
>>
>>> Sin
Hi All,
Please find the version 5 of the patchset that implements firmware-assisted
dump mechanism to capture kernel crash dump for Powerpc architecture. The
firmware-assisted dump is a robust mechanism to get reliable kernel crash
dump with assistance from firmware. This approach does not use kex
From: Mahesh Salgaonkar
Documentation for firmware-assisted dump. This document is based on the
original documentation written for phyp assisted dump by Linas Vepstas
and Manish Ahuja, with few changes to reflect the current implementation.
Change in v3:
- Modified the documentation to reflect i
From: Mahesh Salgaonkar
With the firmware-assisted dump support we don't require a reboot when we
are in second kernel after crash. The second kernel after crash is a normal
kernel boot and has knowledge about entire system RAM with the page tables
initialized for entire system RAM. Hence once th
From: Mahesh Salgaonkar
This patch introduces an sysfs interface '/sys/kernel/fadump_release_mem' to
invalidate the last fadump registration, invalidate '/proc/vmcore', release
the reserved memory for general use and re-register for future kernel dump.
Once the dump is copied to the disk, the use
From: Mahesh Salgaonkar
If dump is active during system reboot, shutdown or halt then invalidate
the fadump registration as it does not get invalidated automatically.
Signed-off-by: Mahesh Salgaonkar
---
arch/powerpc/kernel/setup-common.c |8
1 files changed, 8 insertions(+), 0 de
From: Mahesh Salgaonkar
Introduce a PT_NOTE program header that points to physical address of
vmcoreinfo_note buffer declared in kernel/kexec.c. The vmcoreinfo
note buffer is populated during crash_fadump() at the time of system
crash.
Change in v5:
- Added 'fadump_' prefix to static function re
From: Mahesh Salgaonkar
This patch registers for firmware-assisted dump using rtas token
ibm,configure-kernel-dump. During registration firmware is informed about
the reserved area where it saves the CPU state data, HPTE table and contents
of RMR region at the time of kernel crash. Apart from thi
From: Mahesh Salgaonkar
Build the crash memory range list by traversing through system memory during
the first kernel before we register for firmware-assisted dump. After the
successful dump registration, initialize the elfcore header and populate
PT_LOAD program headers with crash memory ranges.
From: Mahesh Salgaonkar
When registered for firmware assisted dump on powerpc, firmware preserves
the registers for the active CPUs during a system crash. This patch reads
the cpu register data stored in Firmware-assisted dump format (except for
crashing cpu) and converts it into elf notes and up
[My apologies for the resend, it does not seem to have hit the MLs.
I think my git send-email "cc-cmd" may have broken somehow, oops.]
This badly needs breaking up, and a better changelog... oh well...
The big changes:
* The "ppc64_caches" structure is now "powerpc_caches" and is used on
both
From: Mahesh Salgaonkar
Reserve the memory during early boot to preserve CPU state data, HPTE region
and RMR region data in case of kernel crash. At the time of crash, powerpc
firmware will store CPU state data, HPTE region data and move RMR region
data to the reserved memory area.
If the firmwa
Hi Andy,
On Tue, Nov 15, 2011 at 09:06:03AM -0600, Andy Fleming wrote:
> On Nov 14, 2011, at 11:17 PM, Baruch Siach wrote:
> > On Mon, Nov 14, 2011 at 09:04:47PM +, Fleming Andy-AFLEMING wrote:
[snip]
> >> And looking at the p1010si.dtsi, I see that it's automatically there for
> >> you.
>
On Nov 7, 2011, at 2:32 AM, Roy Zang wrote:
> P1023 external IRQ[4:6, 11] do not pin out, but the interrupts are
> shared with PCIe controller.
> The silicon internally ties the interrupts to L, so change the
> IRQ[4:6,11] to high level sensitive for PCIe.
>
> Signed-off-by: Roy Zang
> ---
> ar
On 11/15/2011 03:51 PM, Kumar Gala wrote:
>
> On Nov 7, 2011, at 2:32 AM, Roy Zang wrote:
>
> Should be setting ALL PCIe interrupts to '2'? As I think in general
> we say these PCIe are 'active high'. The only reason I would think
> we would NOT do this is if they are shared with some external
On Mon, 2011-11-14 at 21:32 -0500, Kyle Moffett wrote:
> Unfortunately, I've been staring at PPC asm for long enough that I
> have a migraine headache and I'm going to have to stop here for now.
> If somebody else wants to tackle fixing up the 32-bit copy_page() and
> __copy_tofrom_user() routines
On Mon, 2011-11-14 at 21:32 -0500, Kyle Moffett wrote:
> These functions are only used from one place each. If the cacheable_*
> versions really are more efficient, then those changes should be
> migrated into the common code instead.
>
> NOTE: The old routines are just flat buggy on kernels that
On Mon, 2011-11-14 at 20:36 -0600, Moffett, Kyle D wrote:
> So when you are clearing a whole page, there are only 2 things you can do
> wrong with "dcbz":
>
> (1) Call "dcbz" with an address outside of the page you want to zero.
>
> (2) Omit calls "dcbz" to dcbz for some physical cachelines i
On Tue, 2011-11-15 at 10:22 -0500, Kyle Moffett wrote:
> [My apologies for the resend, it does not seem to have hit the MLs.
> I think my git send-email "cc-cmd" may have broken somehow, oops.]
Or the ML took a while because it's big :-) I got both.
I'll try to review this week. Probably wont get
On Nov 15, 2011, at 17:29, Benjamin Herrenschmidt wrote:
> On Mon, 2011-11-14 at 21:32 -0500, Kyle Moffett wrote:
>> Unfortunately, I've been staring at PPC asm for long enough that I
>> have a migraine headache and I'm going to have to stop here for now.
>> If somebody else wants to tackle fixing
From: Shaohui Xie
Subject: drivers/edac/mpc85xx_edac.c: fix memory controller compatible for edac
compatible in dts has been changed, so the driver needs to be updated
accordingly.
Signed-off-by: Shaohui Xie
Cc: Kumar Gala
Cc: Grant Likely
Cc: Benjamin Herrenschmidt
Signed-off-by: Andrew Mor
On Tue, 2011-11-15 at 16:45 -0600, Moffett, Kyle D wrote:
> I guess that's doable, although I have to admit that idea almost gives
> me more of a headache than trying to fix up the 32-bit ASM.
>
> One thing that bothers me in particular is that both 32/64 versions of
> __copy_tofrom_user() are dr
On Thu, Nov 10, 2011 at 10:13 AM, Kumar Gala wrote:
>
> + lbc: localbus@fffe05000 {
> reg = <0 0xffe05000 0 0x1000>;
> - interrupts = <19 2 0 0>;
I just noticed this bug in the original p1022ds.dts, and I see you're
carrying it over here. The reg property shoul
On Nov 15, 2011, at 18:46, Benjamin Herrenschmidt wrote:
> On Tue, 2011-11-15 at 16:45 -0600, Moffett, Kyle D wrote:
>>
>> With that said, I'm curious about the origin of the PPC32 ASM. In
>> particular, it looks like it was generated by GCC at some point in the
>> distant past, and I'm wondering
On Mon, Nov 14, 2011 at 2:55 AM, Kokoris, Ioannis
wrote:
> Ready register is needed for ROM-less devices such as P1021, MPC859, MPC8306
> etc.
> For ROM-based devices such as MCP8323 the Ready register does not exist.
> Is there a global definition for conditionally including this code?
I'll hav
The Documentation/memory-barriers.txt document requires that atomic
operations that return a value act as a memory barrier both before
and after the actual atomic operation.
Our current implementation doesn't guarantee this. More specifically,
while a load following the isync can not be issued bef
This adds support for p7IOC (and possibly other IODA v1 IO Hubs)
using OPAL v2 interfaces.
We completely take over resource assignment and assign them using an
algorithm that hands out device BARs in a way that makes them fit in
individual segments of the M32 window of the bridge, which enables us
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, November 16, 2011 6:14 AM
> To: Kumar Gala
> Cc: Zang Roy-R61911; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level
> sensitive for PCIe
>
> On 11/15/2011 03:51 PM, Kumar Ga
On Tue, Nov 15, 2011 at 04:45:18PM -0600, Moffett, Kyle D wrote:
> On Nov 15, 2011, at 17:29, Benjamin Herrenschmidt wrote:
> > On Mon, 2011-11-14 at 21:32 -0500, Kyle Moffett wrote:
> >> Unfortunately, I've been staring at PPC asm for long enough that I
> >> have a migraine headache and I'm going
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